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Real-time architectures for 3D video coding

Real-time architectures for 3D video coding

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The previous generation of 3D videos was not appealing enough to justify the support for them in the handheld devices and to maintain this support on other electronic devices, like TVs. The huge amount of data to be transmitted, and limited view synthesis performance resulted in visual discomfort and poor-user experience, which culminated on a momentary stop in the manufacture of those devices. In last years, contrasting with this scenario, emerging 3D-video-related technologies covering 3D-movies, virtual reality, augmented reality, mixed reality, and other technologies, have gained place again in the consumer market, especially in handheld devices. These technologies are driven by devices like Microsoft RealSense 3D, Structure Sensor, and Stereolabs ZED. Most of these devices had focused on a texture plus depth approach, which is the most efficient way to represent/encode 3D-videos nowadays. In this context, 3D-HEVC was published in 2015 adopting the MVD format and novel encoding tools to efficiently deal with MV videos captured by multiple cameras and improved view-synthesis performance. Some works focusing on VLSI designs and the real-time processing of 3D videos can be found in the literature, as discussed in this chapter. Despite the 3D-HEVC being the most efficient way available to encode 3D-videos, video coding in a scenario with multiple views remains to be challenging even considering the 3D-HEVC and dedicated VLSI designs. Then, a few works are available in the literature relating hardware designs targeting specifically the 3D-HEVC tools. Three works were selected to be detailed in this chapter, two of them focusing on the new 3D-HEVC intra-frame prediction tools (DMMs and DIS) and one focusing on the 3D-HEVC inter-frame and inter-view predictions. These three architecture are capable of processing at least HD 1,[email protected] videos in real time. For that, these works developed solutions with different approaches to achieve high throughput with the minimum drawback in area usage and power dissipation.

Chapter Contents:

  • 6.1 3D-high efficiency video coding: a 3D-video-coding standard supporting the multiview plus depth format
  • 6.1.1 Memory, processing, and complexity challenges on 3D-HEVC intra-prediction
  • 6.1.2 Memory, processing, and complexity challenges on 3D-HEVC inter-frame and inter-view predictions
  • 6.2 3D-HEVC real-time architecture for DMM-1 and DMM-4 intra-frame prediction modes
  • 6.2.1 DMM-1 algorithm simplification
  • 6.2.2 Bipartition modes architecture
  • 6.2.3 Synthesis results
  • 6.3 3D-HEVC real-time architecture for DIS intra-frame prediction mode
  • 6.3.1 Depth intra skip algorithm simplification
  • 6.3.2 Depth intra skip architecture
  • 6.3.3 Synthesis results
  • 6.4 3D-HEVC real-time architecture for inter-frame and inter-view predictions
  • 6.4.1 The energy-aware motion and disparity estimation system
  • 6.4.2 Proposed hardware-oriented algorithms
  • 6.4.3 The on-chip memory design and management based on channel aspects
  • 6.4.4 Hardware results
  • 6.5 Conclusions
  • Acknowledgements
  • References

Inspec keywords: video codecs; real-time systems; VLSI; stereo image processing; video coding

Other keywords: MV plus depth; real-time architectures; MV videos; MVD format; 3D-HEVC inter-view predictions; 3D-HEVC inter-frame predictions; high-efficiency video coding; very large scale integration design; encoding tools; three-dimensional videos; 3D-HEVC intra-frame prediction tools; 3D videos; VLSI designs; 3D video coding; multiview video coding

Subjects: Video signal processing; Codecs, coders and decoders; Image and video coding

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