Low-power circuit design techniques for high-resolution video coding

Low-power circuit design techniques for high-resolution video coding

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After an Introduction, the Chapter presents the sources of power dissipation in CMOS circuits, as well as a methodology for accurate power dissipation estimation using real-video data. State-of-the-art low-power techniques used in dedicated hardware accelerator designs are discussed in the next section. One of the methods introduced in this section shows the hybrid encoding of arithmetic operators and a new hybrid-encoded adder operator is presented. The power-efficient hybrid encoding representation groups m bit and uses gray encoding to potentially reduce circuit switching activity, both internally and at the inputs of the arithmetic operators. This section also discusses the exploration of different adder compressor structures in SAD operation and filter interpolation hardware architecture. Adder compressor architecture performs the simultaneous addition of N operands. Combinations of 3-2, 4-2, 5-2, and 7-2 adder compressors are discussed. An approximate computing technique is presented which is based on the coefficient pruning for SATD hardware architecture, and finally the application of the low-power techniques in SAD, SATD, and interpolation filters is presented in detail.

Chapter Contents:

  • 5.1 Introduction
  • 5.2 Power dissipation in CMOS and a methodology estimation using real-video data
  • 5.2.1 Sources of power dissipation
  • Static power
  • Short-circuit power
  • Switching power (dynamic power)
  • 5.2.2 Power estimation in the current industrial ASIC design flow
  • 5.3 Compute-intensive video-coding blocks overview
  • 5.3.1 Sum of absolute differences
  • 5.3.2 Sum of absolute transformed differences
  • 5.3.3 Interpolation filter
  • 5.4 Low-power design techniques
  • 5.4.1 Compression-based operators
  • Internal structures of adder compressors
  • Hierarchical adder compressors
  • 5.4.2 Hybrid encoding
  • Hybrid code definition
  • Hybrid adder
  • 5.4.3 Approximate computing using pruning for SATD
  • Pruning-based algorithm
  • 5.5 Low-power techniques for video-coding blocks—applications and results
  • 5.5.1 SAD block with adders compressors and hybrid adder
  • SAD with adders compressors
  • SAD with hybrid adder
  • 5.5.2 SATD architecture with pruning
  • Results and discussions of the SATD pruning techniques
  • 5.5.3 Interpolation filter with adder compressors
  • Interpolation filters architecture using adder compressors
  • Interpolation filter architecture results
  • 5.6 Conclusions
  • References

Inspec keywords: video coding; integrated circuit design; video codecs; low-power electronics; CMOS integrated circuits

Other keywords: SATD hardware architecture; hardware accelerator designs; low-power circuit design techniques; adder compressor structures; gray encoding; SAD operation; interpolation filters; power-efficient hybrid encoding representation; coefficient pruning; circuit switching activity; hybrid-encoded adder operator; sum of absolute differences; power dissipation; filter interpolation; high-resolution video coding; approximate computing technique; sum of absolute transformed differences; arithmetic operators; CMOS circuits

Subjects: CMOS integrated circuits; Television and video equipment, systems and applications; Codecs, coders and decoders; Image and video coding; Semiconductor integrated circuit design, layout, modelling and testing

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