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## High-throughput architectures for highresolution video coding: hardwired oriented algorithms and VLSI architectures

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High video resolutions along with more complex coding algorithms drive the need for new hardware accelerators featuring high throughputs. Simultaneously, it is desired to achieve this goal at the smallest possible cost of resources and power consumption. In the case of encoders, another important constraint is the allowable loss in the compression efficiency. The efficiency should be close to reference software implementations developed to demonstrate the compression possibilities of a coding standard. These opposite requirements must be satisfied with reference to hardware framework where design units usually support fixed throughputs and delays. Therefore, it is important to develop throughput-balanced processing paths with a high utilization of computation resources. Provided the same performance, encoders are usually much more complex than decoders. Thus, this chapter focuses on hardware-oriented algorithms and architectures dedicated to encoders. However, some design techniques for particular modules can also be applied in decoders. There are some bottlenecks in the encoder dataflow as discussed in Chapter 3. They can be limited or removed by modifications introduced to coding algorithms. Usually, the modifications involve losses in the compression efficiency. The following sections review solutions to particular encoder tasks presented in the literature.

Chapter Contents:

• 4.1 Reconstruction loop
• 4.1.1 Transform architectures
• 4.1.2 Parallel loops
• 4.1.3 Interleaved processing order
• 4.2 Rate – distortion optimization
• 4.2.1 RDO based on signal features
• 4.2.2 Simplified rate estimation
• 4.2.3 Simplified distortion estimation
• 4.3 Intra mode decision
• 4.4 Motion estimation
• 4.4.1 Full search
• 4.4.2 Hierarchical search
• 4.4.3 Test zone search
• 4.5 Entropy coder
• 4.6 Summary
• References

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