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High-throughput architectures for high-resolution video coding: system architecture analysis

High-throughput architectures for high-resolution video coding: system architecture analysis

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In this article discusses the design for high-resolution video involves some challenges, mainly in encoder architectures. First, provided the same algorithm, the amount of computations increases proportionally to the number of processed pixels or to its square. Second, more compression efficient algorithms require more complex architectures. Third, mode and data dependencies between neighboring blocks introduce timing limitations in processing paths, especially in the reconstruction loop. Fourth, architectures operating at higher clock frequencies are indispensable. Fifth, simplifications introduced to algorithms implemented in reference models usually decrease the compression efficiency. Since there are many options and parameters in the encoder algorithm, the space of simplifications is huge. Therefore, designers should decide the algorithm specification subject to target design constraints.

Chapter Contents:

  • 3.1 Hardware vs. software encoders
  • 3.2 Hardware optimization techniques
  • 3.3 Timing constraints on pixel units
  • 3.4 Mode decision tradeoffs
  • 3.4.1 Reconstruction loop
  • 3.4.2 Transforms
  • 3.4.3 Mode preselection
  • 3.4.4 Cost estimation
  • 3.5 Motion estimation and compensation
  • 3.5.1 Search strategy
  • 3.5.2 Fractional-pel motion estimation
  • 3.5.3 Access to memories
  • 3.5.4 Motion vector prediction
  • 3.6 Entropy coding
  • 3.7 Summary
  • References

Inspec keywords: image resolution; video coding

Other keywords: reconstruction loop; system architecture analysis; high-resolution video coding; target design constraints; high-throughput architectures; complex architectures; encoder architectures; neighboring blocks introduce timing limitations; compression efficient algorithms; data dependencies; clock frequencies

Subjects: Video signal processing; Image and video coding

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