Joint algorithm-architecture design of video coding modules
This chapter overviews the joint effort of ITU-T and ISO/IEC to develop the upcoming VVC standard that will outperform HEVC standard by 50% of compression efficiency for similar video quality. Our analysis on current video encoder of VVC reference software (VTM 1) shows that one order-of-magnitude increase in encoding time is expected for VVC encoder compared to HEVC encoder. The complexity growth numbers are expected to increase since the standardization process is still in the beginning and the reference software includes only a small set of coding tools, while others are under test. The BD-rate reduction of VTM 1 compared to HEVC are far from the goal of 50%, but other sophisticated (and complex) coding tools are under test to reach this goal. Monthly meetings are happening to define and test coding tools to be included in each VTM version. The final standard is planned to 2020. This chapter also presented some state-of-the-art solutions on joint algorithm-architecture design of video coding modules, mainly targeted to HEVC, and discussed the challenges on adapting or designing new solutions for VVC standard. The new block partitioning is a key tool that affects many modules, such as RDO, inter- and intra-frame prediction, and transforms. It has also increased the performance requirements because of the rise of possible combinations of block partitioning and coding modes. We foresee that the future video coding systems will need joint algorithm-architecture optimizations by combining fast block partitioning algorithms with high-throughput hardware architecture employing intelligent reusing schemes, fast and low power arithmetic operators implemented in newer technology nodes. These types of challenges on implementing high-throughput hardware modules need to be tackled by industry and academic communities to make the future VVC video-coding standard usable for a wide range of applications.
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