Joint algorithm-architecture design of video coding modules

Joint algorithm-architecture design of video coding modules

For access to this article, please select a purchase option:

Buy chapter PDF
(plus tax if applicable)
Buy Knowledge Pack
10 chapters for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
VLSI Architectures for Future Video Coding — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

This chapter overviews the joint effort of ITU-T and ISO/IEC to develop the upcoming VVC standard that will outperform HEVC standard by 50% of compression efficiency for similar video quality. Our analysis on current video encoder of VVC reference software (VTM 1) shows that one order-of-magnitude increase in encoding time is expected for VVC encoder compared to HEVC encoder. The complexity growth numbers are expected to increase since the standardization process is still in the beginning and the reference software includes only a small set of coding tools, while others are under test. The BD-rate reduction of VTM 1 compared to HEVC are far from the goal of 50%, but other sophisticated (and complex) coding tools are under test to reach this goal. Monthly meetings are happening to define and test coding tools to be included in each VTM version. The final standard is planned to 2020. This chapter also presented some state-of-the-art solutions on joint algorithm-architecture design of video coding modules, mainly targeted to HEVC, and discussed the challenges on adapting or designing new solutions for VVC standard. The new block partitioning is a key tool that affects many modules, such as RDO, inter- and intra-frame prediction, and transforms. It has also increased the performance requirements because of the rise of possible combinations of block partitioning and coding modes. We foresee that the future video coding systems will need joint algorithm-architecture optimizations by combining fast block partitioning algorithms with high-throughput hardware architecture employing intelligent reusing schemes, fast and low power arithmetic operators implemented in newer technology nodes. These types of challenges on implementing high-throughput hardware modules need to be tackled by industry and academic communities to make the future VVC video-coding standard usable for a wide range of applications.

Chapter Contents:

  • 2.1 Introduction
  • 2.2 Video coding evolution and state of the art
  • 2.2.1 Evolution of video coding standards
  • 2.2.2 Overview of HEVC and VVC codecs
  • 2.3 Video coding application analysis
  • 2.3.1 Analysis of VVC and HEVC encoders
  • Compression efficiency
  • Computational effort
  • 2.4 Rate – distortion optimization
  • 2.4.1 Block-partitioning decisions
  • 2.4.2 Distortion metrics
  • Sum of absolute differences
  • Sum of absolute transformed differences
  • 2.4.3 Challenges on rate–distortion optimization for VVC encoder
  • 2.5 Inter-frame prediction
  • 2.5.1 Integer motion estimation
  • 2.5.2 Fractional motion estimation
  • 2.5.3 Dedicated memories for motion estimation
  • 2.6 Intra-frame prediction
  • 2.6.1 Intra-prediction mode decision in H. 265/HEVC
  • 2.6.2 Hardware architecture for the HEVC intra-prediction
  • 2.6.3 Challenges on intra-frame prediction architecture design for VVC encoder
  • 2.7 Transforms
  • 2.7.1 Challenges of transforms architecture design for VVC encoder
  • 2.8 In-loop filter
  • 2.9 Entropy coding
  • 2.9.1 Upcoming challenges related to entropy encoding
  • 2.10 Conclusions
  • Acknowledgements
  • References

Inspec keywords: video coding; optimisation; standards; video codecs; data compression

Other keywords: compression efficiency; fast block partitioning algorithms; high-throughput hardware architecture; VVC reference software; video quality; intelligent reusing schemes; low power arithmetic operators; VVC encoder; VVC standard; ITU-T; VTM 1; video coding modules; coding tools; HEVC standard; encoding time; joint algorithm-architecture design optimizations; ISO-IEC; BD-rate reduction; video encoder

Subjects: Image and video coding; Optimisation techniques; Codecs, coders and decoders; Video signal processing; Optimisation techniques

Preview this chapter:
Zoom in

Joint algorithm-architecture design of video coding modules, Page 1 of 2

| /docserver/preview/fulltext/books/cs/pbcs053e/PBCS053E_ch2-1.gif /docserver/preview/fulltext/books/cs/pbcs053e/PBCS053E_ch2-2.gif

Related content

This is a required field
Please enter a valid email address