Scalable transform architectures for video coding

Scalable transform architectures for video coding

For access to this article, please select a purchase option:

Buy chapter PDF
(plus tax if applicable)
Buy Knowledge Pack
10 chapters for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
VLSI Architectures for Future Video Coding — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

In spite of the recent advances in telecommunication standards, communication networks still have limited bandwidths and storage capacity. Therefore, video compression has drawn increasing importance since high-resolution video contents have become more and more used in various fields. These requirements raise the need for high-performance video-compression technologies able to reduce the amount of data to be transmitted or stored by compressing the input video signal into a bitstream file. Improving the coding efficiency was always one of the crucial issues of various compression standards that aim to get the most compact representation of the reconstructed video, with a high subjective quality. The high-efficiency video coding (HEVC) comes to respond to these requirements. However, the increased consumption of high-quality multimedia content has pushed the international communication companies to put much effort to better enhance video-coding techniques. In this perspective, an upcoming video-coding standard to be known as versatile video coding (VVC) has emerged aiming to improve the coding efficiency of the current HEVC codec. Improvements on rate distortion (RD) performance that came with both HEVC and VVC have brought an increased complexity in the majority of the coding modules, which makes it difficult to implement on hardware systems with real-time encoding. This chapter focuses on the transform coding stage as one of the most computationally demanding modules. For HEVC, efficient approximation algorithms in addition to reconfigurable and scalable architecture have been developed in order to decrease the computational complexity of the transform module. The main objectives are to meet low power and real-time processing constraints while maintaining a compression gain and a satisfying video quality. Field programmable gate array (FPGA) implementation results and comparisons with existing works confirm the efficiency of the proposed approximations since they contribute in reducing time and power consumption, optimizing the hardware resources and bringing peak signal-to noise ratio (PSNR) improvement as well. Similarly, for the adaptive multiple transform (AMT) introduced in the transform module of the VVC, approximations were done for discrete cosine transform (DCT)-II and discrete sine transform (DST)-VII transforms since they are statistically the most used ones among the five predefined types. Bitrate (BR) reduction with a slightly degradation of video quality and a less use of hardware resources are the main contributions of the proposed approximations.

Chapter Contents:

  • 1.1 Introduction
  • 1.2 Review of scalable transforms in HEVC
  • 1.2.1 Transform coding in HEVC
  • 1.2.2 Approximate DCT algorithms and their hardware architecture for HEVC
  • Recursive sparse matrix decomposition
  • Sparse matrix decomposition based on a new 4-point DCT approximation
  • 1.2.3 Complexity analysis
  • 1.2.4 Synthesis results
  • 1.3 Video-coding concept in VVC standard
  • 1.3.1 VVC encoder scheme
  • 1.3.2 Transform coding for VVC standard
  • 1.3.3 Statistical analysis
  • 1.4 Approximation for DCT-II transform and its hardware architecture
  • 1.4.1 Algorithm description
  • 1.4.2 Approximate 8-point transform architecture
  • 1.4.3 Reconfigurable designs for 1D/2D DCT computing
  • Reconfigurable design for 4-and 8-point 1D DCT computing
  • Reconfigurable design for 32-point 1D DCT computing
  • Reconfigurable architecture for 2D approximate DCT computing
  • Reconfigurable architecture for inverse and forward DCT computing
  • 1.4.4 Video-coding performance
  • Simulation conditions
  • Evaluation criteria
  • Results and discussions
  • RD curves
  • 1.5 New approximation for DST-VII transform
  • 1.5.1 Algorithm description
  • 1.5.2 Video-coding performance
  • 1.6 Conclusion
  • References

Inspec keywords: data compression; transform coding; video codecs; field programmable gate arrays; video coding; discrete cosine transforms

Other keywords: high-resolution video contents; approximation algorithms; computationally demanding modules; high-efficiency video coding; coding efficiency; high-performance video-compression technologies; VVC; HEVC codec; input video signal; rate distortion performance; telecommunication standards; hardware resources; compression gain; video quality; transform module; international communication companies; coding modules; compression standards; communication networks; video-coding techniques; high-quality multimedia content; reconstructed video; field programmable gate array implementation

Subjects: Video signal processing; Image and video coding; Integral transforms; Integral transforms

Preview this chapter:
Zoom in

Scalable transform architectures for video coding, Page 1 of 2

| /docserver/preview/fulltext/books/cs/pbcs053e/PBCS053E_ch1-1.gif /docserver/preview/fulltext/books/cs/pbcs053e/PBCS053E_ch1-2.gif

Related content

This is a required field
Please enter a valid email address