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## Modeling of variability and reliability in analog circuits

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Modelling Methodologies in Analogue Integrated Circuit Design — Recommend this title to your library

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This chapter is divided into four sections. In Section 8.1, the probabilistic defect occupancy (PDO) model, a physics-based compact model, is introduced, which can be easily implemented into circuit simulators. Section 8.2 describes a purposely designed IC which contains suitable test structures, together with a full instrumentation system for the massive characterization of TZV and TDV in CMOS transistors, from which aging of the technology under study can be statistically evaluated. Section 8.3 is devoted to a smart methodology, which allows extracting the statistical distributions of the main physical parameters related to TDV from the measurements performed with the instrumentation system. Finally, Section 8.4 describes CASE, a new reliability simulation tool that accounts for TZV and TDV in analog circuits, covering important aspects, such as the device degradation evaluation, by means of stochastic modeling and the link between the device biasing and its degradation. As an example, the shifts of the performance of a Miller operational amplifier related to the device TDV is evaluated using CASE. Finally, in Section 8.5 the main conclusions are summarized.

Chapter Contents:

• 8.1 Modeling of the time-dependent variability in CMOS technologies: the PDO model
• 8.2 Characterization of time zero variability and time-dependent variability in CMOS technologies
• 8.3 Parameter extraction of CMOS aging compact models
• 8.3.1 Description of the method
• 8.3.2 Application examples
• 8.4 CASE: a reliability simulation tool for analog ICs
• 8.4.1 Simulator features
• 8.4.2 TZV and TDV studied in a Miller operational amplifier
• 8.5 Conclusions
• Acknowledgments
• References

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