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Doping-free tunnelling transistors – technology and modelling

Doping-free tunnelling transistors – technology and modelling

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As device dimensions are continuously down-scaling into sub-10 nm regimes, complementary metal-oxide semiconductor technology is facing severe challenges such as increased static power consumption, poor gate controllability, enhanced short-channel effects (SCEs), random dopant fluctuations (RDFs) and process-voltage temperature (PVT) variation, hence, conventional metal-oxide-semiconductor fieldeffect transistors (MOSFETs) have failed to be a worthy candidate for nano-electronics and micro-electronics regime. Recently, the tunnel FETs (TFET) gain tremendous attention because of their low standby power consumption and scalable subthreshold swing (SS). The TFET is a gated P-I-N diode, where ON-state current would be due to band-to-band tunnelling (BTBT) instead of thermionic emission, and they exhibit very low OFF-state current of the order of fA/mm, which makes them a potential candidate for low power consumption. The heavily doped nature of TFETs causes certain problems, and to address them, the concept of dynamically configurable doping-free (DF) TFETs was recently proposed. In this chapter, a detailed analysis of dynamically configurable TFETs such as the working principle, I-Vcharacteristics, fabrication flow and the effect of process and temperature variation is presented.

Chapter Contents:

  • 9.1 Introduction
  • 9.1.1 Scaling of threshold voltage
  • 9.1.2 Need of slow supply voltage (VDD) scaling
  • 9.1.3 Possible solution to the power consumption
  • 9.2 Tunnel field-effect transistor
  • 9.2.1 Operating principle of TFET
  • 9.2.2 The conventional TFET limitations
  • 9.3 DF dynamically configurable TFET
  • 9.3.1 Device structure and simulation parameter
  • 9.3.2 Proposed fabrication process flow
  • 9.4 Simulation results and discussion
  • 9.4.1 Carrier concentration and energy band diagram
  • 9.4.2 Transfer characteristics comparison of conventional and DF-TFET
  • 9.4.3 Output characteristics of conventional and DF-TFET
  • 9.4.4 Impact of supply voltage and PG bias scaling on DF-TFET
  • 9.4.5 Impact of control gate voltage on tunnelling rate and energy barrier width
  • 9.4.6 Impact of source spacer thickness
  • 9.4.7 Sensitivity towards control gate length scaling
  • 9.4.8 Sensitivity towards temperature
  • 9.4.9 Sensitivity towards oxide thickness
  • 9.4.10 Sensitivity towards silicon thickness
  • 9.5 Summary
  • References

Inspec keywords: tunnelling; p-i-n diodes; tunnel field-effect transistors; low-power electronics; nanoelectronics

Other keywords: doping-free tunnelling transistors; MOSFETs; static power consumption; dynamically configurable doping-free TFETs; gated P-I-N diode; device dimensions; TFET; temperature variation; band-to-band tunnelling; BTBT; enhanced short-channel effects; conventional metal-oxide-semiconductor fieldeffect transistor; thermionic emission; tunnel FET gain; complementary metal-oxide semiconductor technology; microelectronics regime; size 10.0 nm; low power consumption; nanoelectronics regime; low standby power consumption; PVT variation; scalable subthreshold swing; fabrication flow; ON-state current; process-voltage temperature variation; random dopant fluctuations; gate controllability; I-Vcharacteristics; low OFF-state current; OFF-state current

Subjects: Junction and barrier diodes; Other field effect devices

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