Your browser does not support JavaScript!

Emerging high-κ dielectrics for nanometer CMOS technologies and memory devices

Emerging high-κ dielectrics for nanometer CMOS technologies and memory devices

For access to this article, please select a purchase option:

Buy chapter PDF
(plus tax if applicable)
Buy Knowledge Pack
10 chapters for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
Advanced Technologies for Next Generation Integrated Circuits — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

The objective of this chapter is to use various electrical characterization techniques to study the interface quality and high-K dielectrics deposited by various process conditions. This provides comprehensive information on the defects, such as density, energy level, time constant and how they interact with other parameters (like flat band voltage, VFB , and dielectric lifetime). Both theoretical model and experimental work are described. Different evaluation methods can provide a good analytical approach to study the dielectrics in the gate stacks. The correlation of experimental data from different methods can enhance the understanding of the defects behavior. Since the next-generation gate dielectrics on high-mobility substrates involve nanoscale devices, it requires a detailed understanding to integrate the technology into standard CMOS technology. Furthermore, this study discusses the advantages and disadvantages of various techniques, since each method has its own limitations such as like sensitivity, range, different extracted parameters, and the difficulty of implementation.

Chapter Contents:

  • 7.1 Introduction
  • 7.2 Historical perspective and current status
  • 7.3 Characterization of Ge/high-κ devices with dry and wet interface treatment
  • 7.4 Interface improvement and reliability of ZrO2/Al2O3/Ge gate stack
  • 7.5 Enhancement of dielectric constant with HfZrO
  • 7.6 Dielectric stacks for next-generation memory devices
  • 7.7 Summary
  • References

Inspec keywords: nanoelectronics; high-k dielectric thin films; CMOS memory circuits

Other keywords: analytical approach; standard CMOS technology; memory devices; evaluation methods; defects behavior; nanometer CMOS technologies; high-k dielectrics; high-mobility substrates; gate stacks; nanoscale devices

Subjects: CMOS integrated circuits; Memory circuits; Dielectric materials and properties

Preview this chapter:
Zoom in

Emerging high-κ dielectrics for nanometer CMOS technologies and memory devices, Page 1 of 2

| /docserver/preview/fulltext/books/cs/pbcs049e/PBCS049E_ch7-1.gif /docserver/preview/fulltext/books/cs/pbcs049e/PBCS049E_ch7-2.gif

Related content

This is a required field
Please enter a valid email address