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## Emerging high-κ dielectrics for nanometer CMOS technologies and memory devices

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The objective of this chapter is to use various electrical characterization techniques to study the interface quality and high-K dielectrics deposited by various process conditions. This provides comprehensive information on the defects, such as density, energy level, time constant and how they interact with other parameters (like flat band voltage, VFB , and dielectric lifetime). Both theoretical model and experimental work are described. Different evaluation methods can provide a good analytical approach to study the dielectrics in the gate stacks. The correlation of experimental data from different methods can enhance the understanding of the defects behavior. Since the next-generation gate dielectrics on high-mobility substrates involve nanoscale devices, it requires a detailed understanding to integrate the technology into standard CMOS technology. Furthermore, this study discusses the advantages and disadvantages of various techniques, since each method has its own limitations such as like sensitivity, range, different extracted parameters, and the difficulty of implementation.

Chapter Contents:

• 7.1 Introduction
• 7.2 Historical perspective and current status
• 7.3 Characterization of Ge/high-κ devices with dry and wet interface treatment
• 7.4 Interface improvement and reliability of ZrO2/Al2O3/Ge gate stack
• 7.5 Enhancement of dielectric constant with HfZrO
• 7.6 Dielectric stacks for next-generation memory devices
• 7.7 Summary
• References

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