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Physical design of polarity controllable transistors

Physical design of polarity controllable transistors

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Functionality-Enhanced Devices An alternative to Moore's Law — Recommend this title to your library

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This chapter deals with the lack of electronic design automation (EDA) tools that would enable industrial adoption of functionally enhanced devices (FEDs), limiting the abilities we have to explore the true potential of these devices. More specifically, we focus on an embodiment of FEDs, namely, silicon nanowire field effect transistors (SiNWFETs) three independent gate FETs (TIGFETs). TIGFETs offer new properties for logic design, including compact XOR and majority gates. We present a tool-flow that utilizes well-known standard EDA tools for synthesis and placement and routing (P&R) in order to map modern real-world designs onto the SiNWFET technology and compare them with current complementary metal-oxide-semiconductor (CMOS) technology. Also, in this chapter, we give emphasis to the concept of structured ASIC (application-specific integrated circuit) (sASIC) design and combine it with the fabrication regularity that SiNWFETs demand. We evaluated the performance of the tool-flow using SiNWFET technology by a series of runs, where the SiNWFET always outperformed the reference technology of FinFETs at 22 nm node, in terms of delay being up to ~35% faster and for exclusive OR (XOR)-dominated designs being ~15% smaller.

Chapter Contents:

  • 9.1 Introduction
  • 9.1.1 IC design and FPGA-ASIC gap
  • 9.1.2 Ambipolar devices for Moore's law extension
  • 9.1.3 Physical design objectives
  • 9.2 Background
  • 9.2.1 Structured ASICs
  • 9.2.1.1 General concept
  • 9.2.1.2 Tile granularity
  • 9.2.2 SiNWFET physical design concepts
  • 9.2.2.1 Sea-of-tiles with SiNWFETs
  • 9.2.2.2 Satisfiable SoT (SATSoT)
  • 9.2.2.3 Power routing of ambipolar designs
  • 9.3 SiNWFET tile layout and placement and routing
  • 9.3.1 Tile configuration for FinFETs
  • 9.3.2 Tile configuration for SiNWFETs
  • 9.3.3 Pin and layout generation
  • 9.3.3.1 Intra-tile connection generation
  • 9.3.3.2 Inter-tile connection generation
  • 9.4 SOCE configuration
  • 9.4.1 Placement schemes
  • 9.4.1.1 Standard cell approach
  • 9.4.1.2 Tile cell approach
  • 9.4.2 Power routing schemes
  • 9.4.2.1 Standard cell power routing scheme
  • 9.4.2.2 Tile cell power routing scheme
  • 9.5 Results and comparisons
  • 9.5.1 Benchmarking methodology
  • 9.5.1.1 Benchmark categories
  • 9.5.1.2 Benchmark summary
  • 9.5.1.3 Performance metrics
  • 9.5.2 Benchmark results
  • 9.5.2.1 Results for control and sequential designs
  • 9.5.2.2 Results for arithmetic combinational designs
  • 9.5.3 Comparisons and conclusions
  • 9.5.3.1 Area increase analysis
  • 9.5.3.2 Speed-up analysis
  • 9.5.3.3 Design interconnection analysis
  • 9.5.3.4 Metal distribution analysis
  • 9.5.3.5 Result summary
  • 9.6 Conclusions
  • References

Inspec keywords: nanoelectronics; logic design; silicon; electronic design automation; CMOS integrated circuits; logic gates; MOSFET; nanowires; digital circuits; elemental semiconductors; application specific integrated circuits; integrated circuit design

Other keywords: SiNWFET technology; FED; logic design; electronic design automation tools; XOR-dominated designs; majority gates; functionally enhanced devices; compact XOR gates; size 22.0 nm; industrial adoption; TIGFET; FinFET; tool-flow; Si; independent gate FET; structured ASIC; modern real-world designs; CMOS technology; polarity controllable transistors; current complementary metal-oxide-semiconductor technology; exclusive OR-dominated designs; standard EDA tools; application-specific integrated circuit; silicon nanowire field effect transistors

Subjects: Digital circuit design, modelling and testing; Logic design methods; Logic and switching circuits; Logic circuits; Insulated gate field effect transistors; Mixed analogue-digital circuits; CMOS integrated circuits

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