Tunnel FET-based security primitive design

Tunnel FET-based security primitive design

For access to this article, please select a purchase option:

Buy chapter PDF
(plus tax if applicable)
Buy Knowledge Pack
10 chapters for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
Functionality-Enhanced Devices An alternative to Moore's Law — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

In this book chapter, we have demonstrated that the usage of emerging transistors, i.e. TFETs, can help improve circuit design resilience against CPA attacks while still preserving low-power consumption compared to their CMOS counterparts. Additionally, besides the traditional criteria for emerging devices such as area, power, delay and non-volatility, security may serve as a new criterion to thoroughly judge the advantages and disadvantages of emerging devices. Using this new standard, we plan to revisit existing emerging transistors to have a full comparison between emerging technologies and CMOS technology. Meanwhile, we believe that more research outcomes are expected in this area where unique properties of emerging transistors can help enhance the security of circuit designs.

Chapter Contents:

  • 13.1 Introduction
  • 13.2 Background
  • 13.2.1 Light-weight cipher
  • 13.2.2 Current mode logic
  • 13.3 Tunnel FET
  • 13.3.1 Device description
  • 13.3.2 Device modeling
  • 13.4 Tunnel FET in hardware security
  • 13.4.1 TFET-based current mode logic
  • 13.4.2 TFET-based CML standard cells
  • 13.4.3 CML implementation on KATAN
  • 13.4.4 Correlation power analysis on KATAN32
  • 13.5 Discussion
  • 13.6 Conclusion
  • Acknowledgment
  • References

Inspec keywords: power consumption; tunnel transistors; low-power electronics; MOSFET; security of data; design engineering

Other keywords: circuit design resilience; circuit security; delay; nonvolatility; tunnel FET-based security primitive design; low-power consumption; TFETs; CPA attacks; power

Subjects: Project and design engineering; Insulated gate field effect transistors

Preview this chapter:
Zoom in

Tunnel FET-based security primitive design, Page 1 of 2

| /docserver/preview/fulltext/books/cs/pbcs039e/PBCS039E_ch13-1.gif /docserver/preview/fulltext/books/cs/pbcs039e/PBCS039E_ch13-2.gif

Related content

This is a required field
Please enter a valid email address