SPICEless RTL design optimization of nanoelectronic digital integrated circuits

SPICEless RTL design optimization of nanoelectronic digital integrated circuits

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The previous chapter discussed various steps of high-level synthesis (HLS) which are used for design exploration of digital integrated circuits. It then discussed specific methods for dynamic power dissipation optimization as well as synthesis of hardware-trojan free digital integrated circuits. The methods relied on various bio-inspired algorithms for design space exploration. As complementary material of the previous chapter, this chapter presents HLS methods for leakage-optimal digital integrated circuit design exploration. Specifically, a paradigm shift approach is presented in which the complete HLS flow is performed without use of any electronic design automation (EDA) tool. All the associated tasks such as modeling, characterization, and optimization are performed using non-EDA tools, and hence this is called the “SPICEless” approach. For a specific objective of nanoelectronic digital integrated circuits, gate-leakage power dissipation is targeted.

Chapter Contents:

  • 9.1 Introduction
  • 9.2 The concept of SPICEless RTL optimization during HLS
  • 9.3 The issues in RTL optimization of power dissipation in digital circuits
  • 9.4 Power optimization at RTL: state-of-the-art
  • 9.4.1. Existing methods for RTL power optimization
  • 9.4.2. Multiple oxide thickness technology for gate-oxide leakage optimization
  • 9.5 A specific SPICEless RTL optimization approach
  • 9.5.1. The overall RTL optimization flow
  • 9.5.2. Objective function for RTL optimization
  • 9.5.3. A specific heuristic algorithm for RTL optimization
  • 9.6 SPICEless characterization of the RTL component library
  • 9.6.1. Gate-oxide leakage modeling
  • 9.6.2. Propagation delay modeling
  • 9.6.3. Analytical modeling of RTL components
  • 9.7 Experimental results for the specific RTL optimization
  • 9.8 Conclusions and future directions of research
  • Acknowledgments
  • References

Inspec keywords: digital integrated circuits; integrated circuit design; electronic design automation; high level synthesis; nanoelectronics

Other keywords: gate-leakage power dissipation; electronic design automation tool; bioinspired algorithm; design space exploration; hardware-trojan free digital integrated circuit; high-level synthesis; dynamic power dissipation optimization; EDA tool; SPICEless RTL design optimization; HLS method; leakage-optimal digital integrated circuit design; nanoelectronic digital integrated circuit; paradigm shift approach

Subjects: Digital circuit design, modelling and testing; Circuits and devices; Nanometre-scale semiconductor fabrication technology; Computer-aided circuit analysis and design

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