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High-level synthesis of digital integrated circuits in the nanoscale mobile electronics era

High-level synthesis of digital integrated circuits in the nanoscale mobile electronics era

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Digital integrated circuits (ICs) are the main workhorse of all modern consumer electronic systems. Digital ICs are much more complex and more closely follow the technology scaling as compared to the analog or mixed-signal ICs. For example, the transistor count can be in billions the device sizes at this point can be 14 nm FinFET in the digital ICs. However, the good news for digital ICs is that the digital designs have well-defined abstractions including system, architecture, logic. This Chapter is focused at the architecture level of the digital ICs. In particular, detailed discussions of high-level synthesis technique has been presented that can generate digital ICs. Trust of electronic systems that are used in day-to-day life is critical. This Chapter also discusses the HLS technique that can generate trusted digital ICs.

Chapter Contents:

  • 8.1 Introduction
  • 8.2 Fundamentals on high level synthesis
  • 8.2.1. Overview on HLS design process
  • 8.2.2. Need for HLS
  • 8.2.3. Scheduling algorithms
  • 8.2.4. Allocation and binding
  • 8.3 Power, energy, or leakage aware HLS for nanoscale ICs
  • 8.3.1. Selected power, energy, or leakage aware HLS methods
  • 8.3.2. Effects of loop manipulation on power and delay of the design
  • 8.3.3. Other design space exploration approaches during HLS
  • 8.4 Bio/nature-inspired algorithms for DSE framework
  • 8.4.1. Selected bio/nature-inspired approaches
  • 8.4.2. A BFOA-exploration process
  • 8.4.3. Encoding/initialization of the datapath bacterium
  • 8.4.4. Encoding of the auxiliary bacterium
  • 8.4.5. Proposed movement of bacterium
  • 8.4.6. Models for metric
  • 8.4.7. Results of the BFOA-exploration process
  • 8.5 HLS approaches for secure information processing
  • 8.5.1. Related work
  • 8.5.2. Exploration process of hardware Trojan secured datapath: security against untrusted third party digital IPs
  • 8.5.2.1 Incorporating vendor allocation procedure 'V' in problem encoding: motivation of exploring this besides datapath resources
  • 8.5.2.2 Evaluation models
  • 8.5.3. Results of exploration process of hardware Trojan secured datapath
  • 8.6 Selected tools available for HLS
  • 8.6.1. Selected commercial tools for HLS
  • 8.6.2. Selected free HLS tools
  • 8.7 Conclusion and future directions of HLS
  • References

Inspec keywords: nanoelectronics; consumer electronics; digital integrated circuits; integrated circuit design; high level synthesis

Other keywords: digital integrated circuits; HLS technique; size 14 nm; FinFET; digital ICs; consumer electronic systems; nanoscale mobile electronics era; transistor count; high-level synthesis technique; digital designs

Subjects: Digital circuit design, modelling and testing

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