Data stability and write ability enhancement techniques for FinFET SRAM circuits

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Data stability and write ability enhancement techniques for FinFET SRAM circuits

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Author(s): Shairfe Muhammad Salahuddin 1  and  Volkan Kursun 1
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Source: Nano-CMOS and Post-CMOS Electronics: Circuits and Design,2016
Publication date April 2016

Six-transistor static random-access memory (6T SRAM) cell is the fundamental building block of memory cache in modern microprocessors. Each bit of data is stored in an individual 6T SRAM cell in the memory subsystem. Read data stability and write ability of 6T SRAM cells are degraded with the scaling of CMOS technology. Conventional circuit techniques for achieving wider voltage margins during read and write operations cause significantly larger silicon area and increased power consumption. Several alternative FinFET memory design techniques are presented in this chapter for achieving stronger data stability during read operations and wider voltage margin during write operations without causing area and power consumption overheads in the memory subsystems of microprocessors.

Chapter Contents:

  • 4.1 Introduction
  • 4.2 Six-FinFET SRAM cells
  • 4.2.1. Conventional six-FinFET SRAM cell
  • 4.2.2. Independent-gate FinFET SRAM cell
  • 4.2.3. SRAM cell with asymmetrically overlap/underlap engineered FinFETs
  • 4.2.4. Hybrid SRAM cell with asymmetrically overlapped/underlapped bitline access transistors
  • 4.2.5. SRAM cell with asymmetrically gate-underlapped transistors
  • 4.2.6. Single-ended read SRAM cell with underlap engineered symmetrical-FinFETs
  • 4.3 Fabrication and SRAM cell area comparison
  • 4.4 Case study: 8KBit memory arrays designed with different SRAM cells
  • 4.4.1. Read static noise margin
  • 4.4.2. Hold static noise margin
  • 4.4.3. Write voltage margin
  • 4.4.4. Data access speed
  • 4.4.5. Leakage power consumption
  • 4.5. Variations of underlap (overlap) lengths due to process imperfections
  • 4.6 Conclusions
  • References

Inspec keywords: power consumption; MOSFET circuits; silicon; SRAM chips; cache storage; microprocessor chips

Other keywords: FinFET memory design technique; 6T SRAM cell; memory cache; memory subsystem; write ability enhancement technique; static random-access memory; microprocessor; power consumption; FinFET SRAM circuit; read data stability; silicon

Subjects: Semiconductor storage; Microprocessors and microcomputers; Semiconductor integrated circuits; Microprocessor chips; Memory circuits

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