Nanoscale FinFET devices for PVT-aware SRAM
This chapter describes nanoscale FinFET devices and their application in SRAM design. It also discusses variability of nanoscale integrated circuits (ICs) and introduces variability-aware memory design. In the previous two chapters, process variations were discussed for analog and digital ICs. However, this chapter focuses on futuristic memory design. A comprehensive variability including process, voltage and temperature (PVT) variations has been discussed for future SRAM design. After analysing the results of PVT-aware designs, it is found that sensitivity-driven IG-FinFET-based SRAM is the most suitable technique for reliable and high-density memories. The design of SRAM using a post-CMOS device, namely FinFET widely adopted in semiconductor industry has been specifically elaborated.
Nanoscale FinFET devices for PVT-aware SRAM, Page 1 of 2
< Previous page Next page > /docserver/preview/fulltext/books/cs/pbcs030e/PBCS030E_ch3-1.gif /docserver/preview/fulltext/books/cs/pbcs030e/PBCS030E_ch3-2.gif