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3D NoC: a promising alternative for tomorrow's nanosystem design

3D NoC: a promising alternative for tomorrow's nanosystem design

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Four primary aspects of chip design are processor, memory, IO, and communication. Communication amalgamated over a SoC (system-on-chip) is the basis of origin of an NoC (network-on-chip). Continuous increase in processing/communication needs with the rapid growth in VLSI industry providing higher and higher integration density within a single die has boosted the step towards this new paradigm shift by the researchers. Advent of three-dimensional (3D) integrated circuits (ICs) design technologies has given this direction another positive thrust. Researchers are indeed very hopeful with the amalgamation of these two different technologies and thereby in developing new methodologies for designing 3D NoCs to cater the need of high-performance nanoscale computing and communication systems tomorrow. This chapter describes different design challenges, available technologies, design and performance issues and parametric measurement of such nanoscale systems, emerging cutting-edge technologies, and possible future directions in designing 3D NoC-based nanosystems.

Chapter Contents:

  • 11.1 Introduction
  • 11.1.1. NoC basics
  • 11.1.2. Transition towards 3D
  • 11.2 Design challenges in 3D NoC
  • 11.2.1. Design challenges
  • 11.2.2. Macro-architecture
  • 11.2.2.1 Micro-architecture
  • 11.2.2.2 Performance
  • 11.2.2.3 Physical design
  • 11.2.2.4 Application mapping
  • 11.2.2.5 Energy-aware modelling and design
  • 11.2.2.6 Thermal issues
  • 11.2.2.7 Reliability analysis
  • 11.2.2.8 Fault tolerance
  • 11.2.3. Emerging technological challenges
  • 11.2.3.1 Wireless NoCs
  • 11.2.3.2 CNT, graphene, and other emerging technologies
  • 11.2.3.3 Photonic NoCs
  • 11.3 Performance centric design of 3D NoCs
  • 11.3.1. Interconnection topology development
  • 11.3.2. Routing policy
  • 11.3.3. Flow control mechanism
  • 11.4 Architectural optimization of 3D NoCs
  • 11.4.1. Router architecture
  • 11.4.2. Network interface controller
  • 11.4.3. Interconnection
  • 11.4.4. Memory
  • 11.5 Thermal-aware design
  • 11.6 Photonic 3D NoC
  • 11.6.1. Photonic interconnect for manycore ICs
  • 11.6.1.1 Photonic devices and systems
  • 11.6.1.2 Systems based on PNoC
  • 11.6.2. Multi-dimensional design issues in 3D PNoC
  • 11.7 Wireless 3D NoC
  • 11.7.1. Low-latency-based wireless 3D NoCs
  • 11.7.2. Inductive coupling interconnected application-specific 3D NoC
  • 11.7.3. Reconfigurable hybrid 3D wireless NoC
  • 11.8 3D NoC simulators
  • 11.8.1. NoC simulation
  • 11.9 Reliability and fault tolerance in 3D NoCs
  • 11.10 Conclusion
  • References

Inspec keywords: three-dimensional integrated circuits; VLSI; integrated circuit design; nanoelectronics; network-on-chip

Other keywords: nanosystem design; high-performance nanoscale computing; three-dimensional integrated circuit design technology; network-on-chip; SoC; communication systems; system-on-chip; 3D NoC design; VLSI industry

Subjects: Network-on-chip; Network-on-chip; Semiconductor integrated circuit design, layout, modelling and testing

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