In this chapter, the key scaling limits are identified for MOS transistors, and methods for improving device performance are discussed. For improved short channel effects, creation of shallow source/dram extension (SDE) profiles, the use of retrograde and halo well profiles to improve leakage characteristics and the effect of scaling the gate oxide thickness are discussed in detail. Experimental data and simulations are used to show that although conventional scaling of junction depths is still possible, increased resistance for junction depths below 30 nm results in performance degradation. Fundamental trade-offs and scaling trends in engineering these effects are analysed.

Inspec keywords: MOSFET

Other keywords: MOS transistor; strain-engineered MOSFET; halo well profiles; device performance; short channel effect; performance degradation; shallow source/dram extension profiles; leakage characteristics

Subjects: Insulated gate field effect transistors