Inspec keywords: network synthesis; clocks; circuit optimisation; clock distribution networks

Other keywords: fast cost computation; benchmark circuits; clock mesh structures; clock resources; clock variation tolerance; SFO problem; reduced clock power; slicing floorplan optimisation problem; for clock spine network synthesis algorithm; clock spine network structures; clock spine exploration; postfix notation

Subjects: Digital circuit design, modelling and testing; Other circuits for digital computers; Other digital circuits