Inspec keywords: multistage interconnection networks; processor scheduling; telecommunication network routing; state feedback

Other keywords: synchronous counterpart; synchronous circuit; CRRD; synchronous concurrent round-robin dispatching algorithm; bundled-data switch; optimal solution; synchronous scheduler; three stage Clos network; high radix switch; asynchronous Clos scheduler; behavioural simulation; unbuffered Clos network; state feedback scheme; asynchronous dispatching algorithm; data path; AD algorithm; asynchronous circuit; asynchronous Clos network routing

Subjects: Communication network design, planning and routing; Communication switching; Multiprocessor interconnection; Multiprocessing systems