Inspec keywords: decoding; cyclic codes; field programmable gate arrays; matrix algebra; parity check codes

Other keywords: repeat accumulate codes; SC-RA codes; FPGA; memory requirements; periodic time variant quasi cyclic algorithm; block memory; optimisation; implementation complexity; memory efficient quasicyclic spatially coupled low density parity check; SC-LDPC codes; QC based approach; parity check matrix; reasonable logic resources; Xilinx field programmable gate array; logic requirements; parity check storage

Subjects: Logic circuits; Codes; Algebra