New Publications are available for Microprocessor chips
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New Publications are available now online for this publication.
Please follow the links to view the publication.Design and development of IGBT resonant inverters for domestic induction heating applications
http://dl-live.theiet.org/content/conferences/10.1049/cp.2012.0360
In this paper, resonant inverters for induction heating are developed for domestic applications. The design is based on half and full bridge single phase inverter of 1 and 4 kW rating. First, the power circuits of the two topologies are analyzed using computer aided design based on Simplorer package. Then, an experimental system was built and tested using microcontroller chip (PiccoloTMS320F28027). The performances of the topologies are highlighted and assessed. The obtained results show that two systems are able to operate satisfactory under soft switching at high frequency with high efficiency. The power control is more interesting for full bridge particularly when the angle phase control is considered. Further, the experimental results agree well with those obtained with the CAD design. This validates the design model used for the purpose. The experimental system shows high integration and flexibility to incorporate other control strategies whereby higher efficiency can be achieved. (6 pages)Real time car theft decline system using ARM processor
http://dl-live.theiet.org/content/conferences/10.1049/ic.2011.0059
Due to the insecure environment the ratio of vehicle theft increases rapidly. Because of this is manufacturers of luxury automobiles has the responsibilities for taking steps to ensure the authorization for the owners and also inbuilt the anti theft system to prevent the car from theft. The existing system was. Car alarm techniques are used to prevent the car theft with the help of different type of sensors like pressure, tilt and shock & door sensors.Drawbacks are cost and cant used to find out the thief, it just prevents the vehicles from loss. The proposed security system for smart cars used to prevent them from loss or theft using Advanced RISC Machine (ARM) processor. It performs the real time user authentication (driver, who starts the car engine) using face recognition, using the Principle Component Analysis - Linear Discreminant Analysis (PCA LDA) algorithm. According to the comparison result (authentic or not), ARM processor triggers certain actions. If the result is not authentic means ARM produces the signal to block the car access (i.e. Produce the interrupt signal to car engine to stop its action) and inform the car owner about the unauthorized access via Multimedia Message Services (MMS) with the help of GSM modem. Also it can be extends to send the current location of the vehicle using the GPS modem as a Short Message Services (SMS) as passive method.GPGPU-accelerated visual search in large surveillance archives
http://dl-live.theiet.org/content/conferences/10.1049/ic.2011.0103
Surveillance archives encompass vast amount of data. Given the amount of data the need for search and data exploration arises naturally. Various authorities such as infrastructure operators and law enforcement agencies are confronted with search needs based on a visual description (size, color, clothing, number plates, facial biometry, etc.) and/or behavioral patterns (limping, loitering, etc.) in order to find a ”needle in a haystack” of digital data. In this paper we present a framework which allows for an efficient video archive forensic search and data exploration in an interactive manner, and exploiting hardware accelerated video analytics at the same time. Furthermore we present a query concept to facilitate and improve the search for a specific person in large video surveillance archives using a synthetic human model in a query-by-example manner. The presented overall framework combines know-how on user interfaces, computer vision algorithms and video archive management. The system is designed with an open archive interface in mind enabling it to operate with CCTV (Closed Circuit Tele Vision) video archives from a wide variety of manufacturers. (6 pages)Implementation of Internet browsing on set top box using ARM-LINUX
http://dl-live.theiet.org/content/conferences/10.1049/ic.2011.0084
There is a need to integrate Internet browsing feature on Set Top Box (STB) as an additional feature to provide value to interactive television services. Even though there are ways to perform such a task, but providing a good design with a capable processor and operating system which are capable of handling more present and futuristic with cost effective looks to be challenging. ARM core processors and Linux operating system (OS) may be employed in implementation of interactive television. ARM is one of the most licensed and thus widespread processor cores in the world and used especially in portable devices due to low power consumption and reasonable performance (MIPS / watt) and Linux is an open source operating system with good flexibility and secured file system. Present paper presents an implementation of Internet browsing embedded in STB using ARM processors and Linux OS.Study of LOD terrain rendering algorithm based on GPU
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0933
Real-time rendering of large scale terrain has always been a hot research topic in the field of computer graphics, virtual reality and simulation research. With scenes becoming more complex and real-time rendering limited, a large number of LOD algorithms have been applied to terrain rendering. In this paper, we review some traditional terrain rendering algorithms, then we show an effective LOD terrain rendering algorithm, and implement it by GPU. At last, we compare those algorithms according to some criterions to show advantages of the algorithm based on GPU.Design and implementation of environmental monitoring system in intelligent home
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0943
Intelligent home is an important part of wisdom urban construction. Home safety, environmental protection and energy efficiency has increasingly become a focus of attention. It is based on such demands, this paper proposes an environmental monitoring system in intelligent home with ATmegal28L as control core, combined with the sensor network technology, to realize information collection, processing and controlling of the internal environment of family, to achieve energy saving and environmental protection and to improve the quality of family living. The tests show that this system works well and has been successful in the Shanghai World Expo Park. It has wide application prospects.GPU accelerated multiplatform FDTD simulator
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0085
In this paper, a few practical pieces of advice for implementing a 3D FDTD algorithm in the OpenCL library are presented. The efficiency of the methods shown is tested by comparing performance of OpenCL 3D FDTD implementation with standard C/C++ implementation.A comprehensive FPGA implementation of collision detection
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0905
The customized hardware platform for collision detection is validly obtained. The components within system are spatial hierarchy constructing block, overlapping test module with pre-projection, pre- masking module for inter-objects collision detection invalidity, parameterized traversing block between geometry elements, graphical processing system on GPU platform and finally optimization block for memory accessing.. Specialized process structures and storage structures are constructed to ensure the stable operation of collision detection system.The design and implementation of elevator monitoring system based on embedded platform
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0796
With the development of urbanization process and residential commercialization, a large number of high-rise buildings have been constructed. With the great increase of elevator quantity, we have to pay more attention to the safety of elevators. The remote elevator monitoring system can provide real-time view of the operating conditions, and control the running of the elevator. This paper is based on C/S (Client/Server) mode. It builds an elevator model based on the embedded development platform of ARM9 EBD9315. At the same time, we capture images with camera and perform JPEG compression to these images, and then transfer images and the elevator running data to control center for real-time display and so on. This paper proposed the elevator monitoring theoretical system, established the system framework, and tested the performance of this model.GPU-based background generation method
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0859
Video processing is wildly used in traffic detection, and it needs a lot of process time of CPU. GPU computing is deeply parallelized and the performance of float-point computing is highly-efficient comparing with the traditional GPU. GPUs are also in cheap price. More and more video processing algorithms are going to add GPU support. This paper describes an effective image background generation algorithm and its GPU implementation. The performance of GPU-based background extraction method is presented. And some issues about its application are discussed as well.Future of computer hardware
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0007
Summary form only given. "Experienced prophets concerning the future." are careful with predictions With this statement in mind, in this paper recent developments in computer hardware are considered along their technical possibilities and limitations. Beyond available standard multicore CPU hardware, this involves the recent impact of specialized accelerator hardware: Currently, general purpose graphic processing units (GPGPUs) and programmable specialized hardware such as FPGA processors or e.g. IBM's Cell processor are successfully used in the field of high-performance computing. This specialized co processor technology gives rise to hybrid-type processors integrating CPU and GPUs. Upcoming candidates for such hybrid-architectures are Intel's "SandyBridge" processor architecture arising from the "Larabee" project, the upcoming systems from AMD including the graphics accelerator technology of ATI Technologies into their CPUS or the future fusion processors recently announced by the companies ARM and NVIDIA under project codename "Denver". The data-level parallelism required for these architecture to achieve suitable high-performance levels has an impact on the development and use of computational electromagnetics (CEM) algorithms and simulation tools: The required use of Single Instruction Multiple Thread (SIMT) operations on massively parallel compute-kernel structures results in a severe performance sensitivity with respect to a controlled flow of the data streams. As a result, these specialized computer architectures will favour numerical schemes which implicitly support these features. High data locality and an intrinsic parallelism usually results in a good ratio between the computational workload for the floating point units (FPUs) and the need for data movement. This can be found e.g. in higher order Discontinuous Galerkin FEM time domain formulations. More generally, discretized field formulations using explicit time integration schemes commonly are easier to parallelize than those based implicit schemes, where complicated solution schemes are required for the algebraic systems of equations involved. Beyond the currently valid paradigm of massive parallelism which follows several decades of a steady increase in the average wall-clock speed of CPU architectures, current research on computational architectures also focuses on reconfigurable systems. First systems using hybrid-core computing by CPUs with programmable FPGAs are becoming available and are already in use for data intensive applications. Future systems featuring fully reconfigurable special-purpose cores that are capable to adapt to the computational task at hand are currently under development. The possible full impact of such reconfigurable core systems to the field of computational electromagnetics is yet an open subject to speculation, although some research results on FDTD implementations hard-coded on FPGAs have been published already in the past recent years. Another important topic to be addressed with future computer hardware is the need to optimize the ratio of computational performance in relation to the electric power consumption (Flop per Watt): On a technical system level, a high electric power density is cause for concern because of resulting thermal stresses and often results in the need for expensive cooling measures. On a macroscopic economical level, the costs of the electric energy consumption of the computer system itself and its external cooling systems result in increasing total costs of ownership (TCO). With an increasing need for very large scale CEM computations e.g. in computational electromagnetic compatibility testing, these TCO costs are no longer negligible even for medium scale compute-clusters in an industrial or research environment. In addition, the reduction of electric energy consumption of the compute cores is an essential technical necessity in the design of future high-performance computer systems in the exa-flop scale. With these future super computers to be available approximately in 2018 (following Moore's law) the contemporary peta-flop super computers are to be exceeded in terms of computational performance by three orders magnitude, but they may not so exceed these in terms of electric energy consumption.Design and analysis of an intelligent collision avoidance system for locomotives
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0481
Railways provide a better alternative to other modes of transport by being energy efficient since it can carry large number of people and goods at the same time. In the recent years, number of accident due to trains are more and the losses also heavy. The main reason for these accidents is irresponsibility of driver and signalling problems which results severe damage to life and property. We have proposed a new method called Intelligent Collision Avoidance System (ICAS) for avoiding frontal collision. This system avoids the collision in an efficient way by notifying the status of two trains in the same track when they are separated by three kilo meters. This is done by warning the driver both visually and by giving a sound alert. The ICAS will manage situations efficiently and notify the opposite train which is on the same track. We have designed a new vibration sensor for sensing the train on the track. Analyses of channel model for different geographical area are discussed. The prototype is designed using micro controller and tested successfully through wireless communication.A low area clipping engine in 3D graphics system
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0936
With the development of computer graphics, the requirement of using assistant hardware to enhance the efficiency of GPU becomes more and more popular. In this paper, we present a low area algorithm to implement a dual-path clipping engine, which is placed in geometry module. It has a lower area compared with previous algorithms by adapting the calculation interpolation unit. Ultimately, we evaluate this algorithm on Xilinx virtex2 FPGA platform.Automation of PV farmers pump
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0354
The primary aim of this project is to develop and atomize the PV farmers pump considering the power supply, direct current (DC), Alternating current (AC), inverter frequency, GSM technology, a well, water level in the well, submersible monoblock pump. Here we introduce an advanced technique with GSM (Global Service for Mobile communication) module. The PV farmers pump which work by utilizing the energy from the SOLAR ARRAYS and the power from the PV panel are stored in a battery. The power from the battery is inverted and given to the pump for irrigation. This pump is also controlled by the GSM module. The use of GSM mode is to start and stop working of pumps using mobile phone; the water level monitoring is also done by the GSM mode which this also provides the message the status for each hour. This is done with the embedded C in PIC16F877A microcontroller. The main advantage of this project is optimizing the power and also saving government's free subsidiary electricity (22% of total power production in India). This proves an efficient and economy way of irrigation and this will automate the agriculture sector.Designed and implemented of graphics rasterization algorithm with FPGA
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0902
The rasterization stage, which is an important part of a graphics processing unit, always requires huge operations and is the bottleneck of the performance, especially for mobile devices. In this paper, the authors research the rasterization algorithm and optimize some rasterization algorithm. In the last, the authors implement a simple rasterization engine with small hardware resource of FPGA.D.C. motor control
http://dl-live.theiet.org/content/conferences/10.1049/ic.2010.0189
Control systems for d.c. traction motors are well established. The developments in power converters, particularly GTO thyristors and IGBTs, and the use of microprocessor controllers have produced control systems which offer a wide and flexible control range with efficient power conversion, whilst utilising relatively simple control techniques. The main limitation is the motor commutator which requires maintenance and restricts high speed performance. However, the continuing developments in a.c. induction motor control systems are resulting in the railway industry increasing its use of this technology. Although this trend will continue, there are a large number of vehicles fitted with d.c. motors and electromechanical controllers. In order to increase the life of such equipment, it has been found economical to upgrade the control systems using techniques which have been described here. Such systems are likely to be in use for many years in the future.The impact of neural model resolution on hardware spiking neural network behaviour
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0515
This paper contributes to the development of the proposed EMBRACE mixed-signal, reconfigurable, Network-on-Chip based hardware Spiking Neural Network. EMBRACE-FPGA is an FPGA-based prototype of the proposed EMBRACE architecture. Results from successful evolution of an EMBRACE-FPGA SNN robotics controller are presented. Noise in best fitness plots for a range of evolved EMBRACE-FPGA based SNN applications, including the robotics controller, have been observed. This paper investigates the sources of neural noise, and considers their impact in evolving digital-based hardware SNNs. The paper considers the expected performance benefits of the EMBRACE analogue neural cell.Impact of simultanous switching noise on packaged mixed SoC [simultanous read simultaneous]
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0653
Increasing numbers of high-density and high-speed mixed circuits has been integrated on a single chip, while the devices are becoming more sensitive to the simultanous switching noise. In this paper,a chip-package co-design method is presented for co-design of chip and package. Based on the analysis of simulation result of package and chip, a special circuit which is composed of resistors and capacitor is designed on chip to decrease the affect of simultaneous switch noise. The simulation shows an excellent agreement with measurement within a 1% margin.A fully integrated SoC for large scale wireless sensor networks in 0.18 μm CMOS
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.1034
A fully integrated system-on-chip (SoC) intended for use in large scale wireless sensor networks is built in 0.18um CMOS. All of building blocks including embedded microprocessor ARM7TDMI, baseband modem, radio transceiver, ADC/DAC, temperature sensor and some communication ports have been integrated into a single chip. The baseband modem adopts BPSK/QPSK DSSS modulation, which symbol rate and processing gain are optional. The radio transmitter utilizes the direct modulation scheme while the receiver is based on Low-IF architecture which Rx sensitivity can achieve -92dBm. The temperature sensor on chip can provide a resolution of 0.15°C from -55°C to + 130°C with an error of less than 0.7°C.System level simulation of RF SoC
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0652
The challenges for next generation wireless systems will increase even further, when designs must be targeted to multi-standard and re-configurability requirements. The ideal software-defined radio architecture is introduced and the practical limitations of current technology are highlighted, which make this architecture currently unrealizable. A structure of RF SOC is presented. To simulate the bit-error-rate (BER) and eye diagrams of a complete receiver link, we combine MATLAB/Simulink modeling and simulation capabilities with the analog simulation capability of AMS. This co-simulation process allows users to easily perform system level test on the analog circuit being designed.Implementation of an IO-Link interface library component for SoC applications
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0516
IO-Link is a new point-to-point communication and connectivity protocol between a master and a sensor/actuator (device), using which it is possible to transfer serial data by way of switching output, using only 3 wires. Till date this protocol has been implemented using generic μCs. In this work a custom model of the Data Link Layer (DLL) of an IO-Link device is proposed. This DLL is able to handle parameter data exchange with the master. Other than the advantages of less chip area and liberty of defining the clock-rate, this model can be used as a library component for future single-chip solutions of IO-Link devices. So this work is primarily a study project on the DLL of IO-Link devices and investigation has been done on its hardware complexity and implementation capability.Communication between industrial computer and micro-energy pulse power supply with nanosecond pulse width
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.1334
In the paper, a communication circuitry is constructed between industry personal computer and micro-energy pulse power supply with nanosecond pulse width. A single chip microcomputer belonging to C8051F series which can deal with both analog signals and digital signals is adopted. The chip is of universal asynchronous receiver transmitter (UART) which is an enhanced serial port with frame error detection and address recognition hardware. The UART are assigned Port pins in a priority order by configuring the special crossbar. The serial bus is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little intervention by the CPU. The serial bus does not share resources such as timers, interrupts, or Port I/O. Then, the communication soft is developed based on silicon laboratories IDE and Microsoft Visual C++. The micro-energy pulse power supply may be controlled by industry personal computer.Design and implementation of a SoC-based security coprocessor and program protection mechanism for WSN
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.1044
The practical applications of wireless sensor networks in vulnerable areas require the communication data of sensor devices confidentiality, integrity and freshness. Furthermore the program data of sensor devices need to be protected. In this paper, we present the design, implementation and simulation of an effective hardware security coprocessor namely RC5-FKM and program protection mechanism based on system on chip (SoC) technology for wireless sensor networks (WSN). Compared with existing works, the unique features of our design includes: (1) a design of fingerprint based key management (FKM) is implemented in SoC, which is used to build secret keys for cryptographic coprocessor. (2) A program protection mechanism is proposed to prevent the program data from being read out by system intruders so as to improve the security of program data in sensor device. (3) A reusable optimized logic cell (ROTL) including some adders and registers is implemented in RC5-FKM, which results in the elimination or minimization of the additional hardware overhead. The design is mapped on FPGA and ASIC design. Results show that the hardware overhead of our design is 9.6% less than previous designs and the execution time of our hardware design is only 0.2% of that of general processors and shorter than other AES coprocessors.Design of ZigBee-based wireless control system of circulating water concentration ratio
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.1038
This article introduced the wireless sensors and wireless actuators combined of ZigBee wireless transmission with sensor or actuator, and its application in circulating water concentration rate control system. Starting with the system topology, it introduced the CC2430 microcontroller and ZigBee features detailed design process of hardware and software in the system, including interface circuit, and each part initial setup, data acquisition and control, and a detailed discussion system design problems.A configurable FFT Processor
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0662
In this paper, a configurable FFT processor is presented which can be configured as 8192 point, 4096 point, 2048 point and 1024 point FFT processor. The processor is based on mixed radix algorithm and single-path delay feedback(SDF) architecture is adopted. The configurable architecture is achieved by connecting or bypassing specific processing elements. To improve processor performance, a dynamic scaling approach is adopted and internal data is formatted as self-defined floating point, and the arithmetic for the self-defined floating point is simple. The experiment results show that the approach can achieve high and constant SNR. The processor is implemented on FPGA.Congestion-and energy-aware run-time mapping for tile-based network-on-chip architecture
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0578
The mapping of application tasks to processing elements (PE) connected by a network-on-chip (NoC) has a significant impact on the overall performance and power consumption of the applications. In this work, a novel dynamic task mapping algorithm is proposed to reduce the overall latency and power consumption of a given set of applications. Applications are modeled by task graphs. Each task graph represents a application and is composed of several tasks. A task is mapped as close to its parent task as possible, based on a candidate spiral search (CSS) method for candidate PEs. The CSS starts to search an empty PE for mapping the requested task with the Manhattan distance between the requested task and its parent task is equal to one. If there is not any candidate available, the Manhattan distance is increased by one until an empty PE is found. Further, the aggregate communication load (ACL) of each candidate PE is also monitored. A task is primarily mapped to a candidate PE which is in the candidate set found by CSS with the minimal ACL. The proposed Rotating Mapping Algorithm (RMA) thus employs CSS to reduce communication latency and ACL to achieve load balancing, which implies lower power consumption. Experiments demonstrate the feasibility and benefits of the proposed method compared with some state-of-the-art task mapping techniques. The Proposed algorithm at most reduces 42.73% in the total energy consumption and 29.32% in the global average delay.Low power application specific processor for ISM band transceiver
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0525
A low power integrated transceiver incorporating a full Industrial Scientific Medical (ISM) band low IF transmitter and receiver with an application specific RISC processor design is described. The RISC processor contains hardware acceleration blocks, including parallel-to-serial, timers, 8B10B endec and an AES cryptographic accelerator. Application specific microcode allows the device to be tailored for different applications through a single custom mask. The design is fabricated on 0.18um CMOS. Measurements and results from prototype silicon are presented.An evolvable NoC-based spiking neural network architecture
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.1732
Nature employs bio-inspired concepts such as evolution and learning to develop complex and intelligent organisms, capable of adaptation and fault tolerance. Brain-inspired paradigms such as Spiking Neural Networks (SNNs) offer the potential of elegant, low-power and robust methods of performing computing. Previous work by the authors reports a reconfigurable mixed signal Network on Chip (NoC)-based SNN architecture, with reconfigurable analogue neuron cell and digital NoC The SNN architecture includes an array of neural tiles, each incorporating a NoC router for packet-based neuron interconnect. This paper presents a Genetic Algorithm (GA) based evolution framework which interacts with the SNN architecture to evolve SNN-based solutions to problems. Simulation results are presented which verify the adaptability of the reconfigurable NoC-based SNN architecture in evolving a solution for the XOR benchmark problem. Results on the synthesised neural tile area utilisation for FPGAs are also presented. This work contributes to the realisation of a large scale reconfigurable mixed signal hardware platform for SNNs. (6 pages)ASIC implementation of a finite field arithmetic processor core
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.1722
In this paper, an ASIC implementation of a processor for generic computations of the type u = ab/c in the Galois field GF(2<sup xmlns="http://pub2web.metastore.ingenta.com/ns/">m</sup>) is described. This algorithm can perform the operations in an Elliptic Curve Crypto (ECC) processor. In this case the hardware operates in the field defined by a given irreducible polynomial. The area and timing performance of the processor are discussed for a 0.35 μm ASIC technology. (6 pages)Application of real-time signal processing in chirp scaling SAR imaging
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.0363
In order to meet the challenges of space-borne SAR real-time imaging, a two-processor chirp scaling SAR processing cluster is currently under research and development. First, this paper focuses on the optimizing of real-time imaging processing method based on deep analysis of CSA and Doppler parameter estimation algorithm. And then, different levels of parallel processing technique on hardware are discussed. The experiment is performed on real space-borne SAR echo data block (16384*16384) and the whole progress is completed within 41s. The design and implementation concept of this highly flexible SAR processing cluster can be extended to other platform. (4 pages)Iris image quality assessment based on FPGA coprocessor
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.2013
The quality of iris image is a key point to affect the accuracy of iris recognition system. There are four main abnormities of captured iris image: defocus, motion blur, eyelid occlusion and eyelash occlusion. They can be distinguished by comparing different frequency components of the image. This paper describes a technique of using Field Programmable Gate Arrays (FPGA) coprocessor to assess the quality of the iris image in a Texas Instrument (TI) Digital Signal Processor (DSP) based Iris Recognition System, by implementing Laplacian Sharpening and 2D-FET transform on the chip. FPGA has become an extremely cost-effective mean of computing algorithms to improve system performance and enhance the computation capability and flexibility of the iris recognition system based on DSP.Test scheduling of SOC IP interconnect for static and SI faults
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.1900
This paper proposes a scheduling method of SOC (System on Chip) interconnect test complied with IEEE Std 1500 based on Genetic Algorithm. The algorithm figures out optimal scheduling of interconnect test for high utility of TAM (Test Access Mechanism) width, and eight fixed test patterns are used to cover static and Signal Integrity faults based on MA (Maximum Aggressor faults model) for specific victim. Experiment is implemented in ITC'02 benchmark to prove the effectiveness of the algorithm solved with MATLAB toolbox.Research on pipeline R2<sup xmlns="http://pub2web.metastore.ingenta.com/ns/">2</sup>SDF FFT
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.0174
The resource utilization of butterflies, multipliers, memory size, and control logic was analyzed according to several pipeline FFT processors. Radix-2<sup xmlns="http://pub2web.metastore.ingenta.com/ns/">2</sup> Single-path Delay Feedback (R2<sup xmlns="http://pub2web.metastore.ingenta.com/ns/">2</sup>SDF) was proposed due to the limit of hardware resource and real-time in ASIC design; gave the scheme, pipeline architecture, flow of BFI and BFII; did Signal to Quantization Noise Ratio (SQNR) simulation for various bit-widths, round or cut off deal per stage, different input/output word lengths; implemented in Xilinx series FPGA V4SX55 with VHDL, did pulse compression in one radar project to verify R2<sup xmlns="http://pub2web.metastore.ingenta.com/ns/">2</sup>SDF algorithm; R2<sup xmlns="http://pub2web.metastore.ingenta.com/ns/">2</sup>SDF FFT need the least resource, has high real-time performance, is suitable for VLSI implementation. (5 pages)Dynamic reconfigurable storage and pretreatment system of SAR signal processing using Nios II architecture
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.0424
Because of synthetic aperture radar (SAR) is a powerful remote sensing technique, there has been growing interest in using SAR to obtain high resolution image. Modern high- performance SAR requires advanced and sophisticated signal processing technique to get high-quality image products. Meanwhile, the semiconductor technologies are updated day after day, programmability and flexibility are the trend of current electronic system, and it leads to the advent of system-on-chip (SOC). The Nios II, a soft-core processor integrated in Altera FPGA chip, is characterized by its flexibility and programmability. In this paper, a dynamic reconfigurable storage and pretreatment system of SAR signal processing is designed and realized based on the Nios II soft-core processor. The proposed architecture takes advantage of the embedded CPU to control all the peripherals, highly increased the efficiency of the design. (4 pages)Design of high-performance session management module in network behavior inspection system
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.2001
Network management system is required to have high-performance as well as good functionality since the Internet traffic is increasing rapidly. This paper presents a design of network behavior inspection system based on PowerPC network processor and embedded Linux. To ensure the high performance of the system, the implementation of the session management module is based on the table lookup unit (TLU) of the network processor. Experimental result shows there is a substantial increase in the efficiency of the session management.Scheduling of balancing WSC for minimum IP testing time
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.2000
Today the research on designing for testability is becoming very important in the filed of SoC. However, the traditional research is limited in top level of SoC. It does not really guarantee to improve the utilization of test resource of SoC and reduce the test time effectively in theory. This paper proposes that the focus of study will be extended to the IP core level. We can reduce the percentage of idle test time and achieve the minimum of test time in various IP cores through the establishment of scheduling strategy of balancing WSC (Wrapper Scan Chain) and the exchange ISC (Inter Scan Chain) heuristic algorithm. In this paper, we verify the scheduling strategy of balancing WSC in algorithm and reusability upon the ITC'02 benchmarks. The results show that the vast majority of percentage of idle test time is much less than 1 % in the relationship set between the number m of balanced WSC and the test time Γιρ within each IP core. The results also can verify the importance of the research programme which is implemented in IP core level for improving the utilization of test resource and reducing the test time effectively in SOC.Determining fundamental frequency of a periodic signal on an 8-bit platform
http://dl-live.theiet.org/content/conferences/10.1049/ic.2009.0173
The proposed implementation performs fundamental frequency estimation on an 8-bit general purpose microcontroller. This achieved by implementing autocorrelation on a periodic wave obtained from single source. Implementation of fundamental frequency estimation methods on microcontrollers will ease the designing in lowlevel applications. Fundamental frequency estimation is mistaken by pitch detection. But the pitch is perceived as combination of all the frequency present in the wave and is related more to the perception of the brain. The result of the autocorrelation function obtained from the microcontroller is compared with the one obtained by PC. The autocorrelation and FFT is compared owing to the large popularity of the latter. (4 pages)Implementing complex and multiple DSP systems on chip: developing a "tops-down" approach to multicore processor architectures
http://dl-live.theiet.org/content/conferences/10.1049/ic_20080611
TI has over a decade of successful history in multi-core processor and system-on-chip (SoC) design. A generic bottom-up SoC architecture approach will be compared to application-domain focussed various multi-core architectures. Heterogeneous designs will be compared to homogeneous solutions. Various performance indicators will be discussed, such as application scope, design challenges, power consumption and development tool chains. The talk will close by addressing some current-day virtualization challenges in multi-core processor design. (16 pages)Analyzing simulated annealing using random models
http://dl-live.theiet.org/content/conferences/10.1049/ic_20080299
The development of online algorithms has harnessed multi-processors, and current trends suggest that the understanding of systems will soon emerge. Given the current status of linear-time technology, cyberneticists shockingly desire the investigation of hash tables. In order to fulfill the purpose, it is concluded not only that wide-area networks and replication are generally incompatible, but that the same is true for massive multiplayer online role-playing games.Designing heterogeneous systems including programmable hardware, multicore processors, DSP, processors and more
http://dl-live.theiet.org/content/conferences/10.1049/ic_20080616
Designers working with programmable hardware can choose from a wide selection of platforms including off-the-shelf, custom or application-specific, field-programmable, configurable and many other products and devices. The range of options and distinct application requirements is growing and designers have to understand and distinguish between the options available to them. In this talk, Chris draws upon his wide-ranging knowledge of the semiconductor industry, differing application markets ranging from consumer to defence and experience from Cambridge Consultants' projects to offer some insight into the platform choices available; how they may be differentiated and how an investment in them might be protected given the level of engineering development and product life-cycle challenges that must be met. Further observations offered regarding market trends, choice of computation model, program memory system, development and verification tools and sourcing underlying intellectual property. (27 pages)Exploiting the SoC capability of high performance FPGAs - a video case study
http://dl-live.theiet.org/content/conferences/10.1049/ic_20080613
As high performance applications become increasingly complex, reconfigurable computing must evolve to address the industry's shifting needs. Multi-layered FPGA SoC platforms can enable rapid system development and provide the designer with control over their own differentiating IP. This presentation will describe the key challenges faced by today's video system designers and how FPGA technologies can deliver both fast time to market and high performance processing. Specifically, a video framework is described targeting representative multi-stream video processing applications. (24 pages)Energy-aware compilation for network processors: frameworks, techniques and trend
http://dl-live.theiet.org/content/conferences/10.1049/cp_20080820
To feed the increasing need for higher network processing line-rate and easier network application development, compilation for Network Processors (NP) has been a hotspot in research. Bit-stream-oriented programming, multiple processing units and heterogeneous architectures all make the job of an NP compiler complicated. Meanwhile, energy efficiency has also become a heated issue while parallel NP system is becoming more powerful and power-hungry. This paper comprehensively reviews NP compilation techniques and energy-aware optimizations. It focuses on the classification in respect of NP compiler's parallel packet processing capability, and the energy-aware optimizations in all compilation stages. In the end, it concludes with the predicted research trends in the NP compilation area.An optimal IEEE 1500 core wrapper design for improved test access and reduced test time
http://dl-live.theiet.org/content/conferences/10.1049/cp_20080663
IEEE 1500 test wrappers that enable higher test bandwidth capability, system bus connectivity and efficient test vector organization are presented. Embedded core wrappers and test vectors that seamlessly work with ASIC and FPGA design flows are illustrated. Implementation and test-chip design show the positive impact on test time with potential for minimal wiring and logic overhead savings.Proposed architecture of configurable, adaptable SoC
http://dl-live.theiet.org/content/conferences/10.1049/cp_20080690
To study the concept of Self Adaptive Networked computing Elements (SANE) we developed a configurable platform based on the Xilinx EDK and Xilinx System Generator tools. The platform is built around a MicroBlaze CPU with a set of standard peripherals such as DDR RAM controller and RS232 interface - denoted as "Master", extended with a set of several "reprogrammable Accelerators" connected to the MicroBlaze "Master" via fast simplex links (FSL).Adaptivity and reliability in future chips: multi-core and reconfigurable architectures in the nano era
http://dl-live.theiet.org/content/conferences/10.1049/cp_20080629
Summary form only given. The field of embedded electronic systems is still emerging. Multipurpose adaptivity and reliability features are playing more and more of a central role, especially while scaling silicon technologies down according to Moore's benchmarks. Leading processor and mainframe companies are gaining more awareness of reconfigurable computing technologies due to increasing energy and cost constraints. The author's view is of an "all-win-symbiosis" of future silicon- based processor technologies and reconfigurable circuits/architectures. Dynamic and partial reconfiguration has progressed from academic labs to industry research and development groups, providing high adaptivity for a range of applications and situations. Reliability, failure-redundancy and run-time adaptivity using real-time hardware reconfiguration are important aspects for current and future systems. Thus, scalability, as we have experienced for the last 35 years is at its end as we enter the so-called Nano Era. Beyond the capabilities of traditional reconfigurable fabrics (like FPGAs), nano circuits/architectures allow for micro-mechanical switches that enable new memory and reconfiguration technologies with the advantage of online chip adaptivity and non-volatility. The deployment of new 3-D nano structures and materials promises higher integration densities and is considered advantageous for signal delays. Yield is significantly lower, and could, as we define it in the classical sense, eventually be nil! Transient faults may lead to unreliable information processing as information in nano-sized devices is much less. Power consumption and related problems present a challenge where information is processed within a smaller area/volume budget. Thus, novel design methodologies, novel adaptive mechanisms which solve operation-time shortcomings, and novel computing paradigms are necessary. Fault tolerance/correction in all its facets is key and should be considered an inherent technique in any nano design/synthesis step. This paper discusses challenges and outlines some promising perspectives for future multi-core and reconfigurable dynamic, complex, adaptive and reliable systems-on-chip, for embedded and general purpose systems.Recent advances in COTS architectures applied to avionics
http://dl-live.theiet.org/content/conferences/10.1049/ic.2007.1668
Presents a collection of slides covering the following topics: COTS architecture; military electronics; military system; open system; plastic encapsulation; weapon system; logistics improvement; integrated circuit; microelectronics chip; CMOS development; neutron collision; multicore processor; and graphical editor.A novel CMOS string D/A converter for system-on-chip applications
http://dl-live.theiet.org/content/conferences/10.1049/cp_20070740
The once emerging trend of silicon-on-chip is becoming a reality. The challenge of integrating a digital-to-analog converter on a single chip is one of the bottlenecks in SoC solutions. A threshold inverter quantization (TIQ) architecture is proposed in this paper for a design of a novel string D/A converter. The so-called TIQ is based on the principle that the threshold voltage of an inverter can be manipulated by altering the layout geometry. The new design technique of D/A converters presented in this paper could achieve a significant improvement on both speed and layout area aspects. A 4-bit TIQ based string demonstrator DAC has been designed using a 0.7 micron standard CMOS technology. This demonstrator DAC can achieve a maximum speed of 425 MSPs which is 2 orders higher than the typical commercial use DAC.A novel and powerful TCAD methodology to evaluate performance of ESD protection devices
http://dl-live.theiet.org/content/conferences/10.1049/cp_20070677
On-chip electrostatic discharge (ESD) protection requires not only extensive technical experience but also scientific technology computer aided design (TCAD) methodology for evaluation. A novel and powerful TCAD methodology aimed to evaluate performance of ESD protection devices objectively is developed and presented. Mix-mode transient circuit simulation, which depicts ESD events better, is acquired in this simulation method. This TCAD methodology pays more attentions to the transient behaviors and characteristics of ESD protection devices which are more valuable to predict performance of ESD protection devices. This TCAD methodology with good ability of convergence can evaluate the performance of ESD protection devices scientificly and has strong direction ability to the design of ESD protection devices.Software/hardware codesign for H.264/AVC bit stream decoding
http://dl-live.theiet.org/content/conferences/10.1049/cp_20070721
Based on the co-design of software/hardware, we studied the method of bit operation instruction extension to enhance the efficiency of H.264 bit stream decoding. Then we gave the implement circuits of bit operation instructions as a coprocessor, and integrated it into the RISC3200 processor. Experiment results show that about 50 cycles are saved on RISC3200 with bit operation instructions for each bit decoding of H.264 bit stream.ASIP: developments, challenges and trends
http://dl-live.theiet.org/content/conferences/10.1049/cp_20070790
Application Specific instruction Set Processor (ASIP) becomes an attractive substitute for ASIC as transistor density, logic complexity and market competition boost. Similar to ASIC, ASIP is based on customized and tailored architectures. In this way, ASIP delivers high performances with low overheads on cost and power whilst taking the advantages of high flexibility and fast time-to-market as a processor-based solution. To demonstrate this effective solution for embedded applications, this paper performs an overall investigation on ASIP's developments, challenges, trends in terms of architectures and design methodologies.