New Publications are available for Logic and switching circuits
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New Publications are available now online for this publication.
Please follow the links to view the publication.Implementation and testing of multipliers using reversible logic
http://dl-live.theiet.org/content/conferences/10.1049/ic.2011.0073
Reversible logic gates are very much in demand for the future computing technologies as they are known to produce zero power dissipation under ideal conditions. Reversible logic circuits are of interests to power minimization having applications in low power CMOS design, optical information processing DNA computing, bio informatics, quantum computing and nanotechnology. Both reversible logic synthesis and testing reversible logic circuits are very important issues in this area. Multipliers are very essential for the construction of various computational units of a quantum computer. Multiplier is an important hardware unit that decides the speed in any processor. In this work, an unsigned four bit array multiplier and signed Baugh-Wooley multiplier circuits using reversible gates are implemented. A reversible Built In Logic Block Observer (BILBO) is also designed by using which the proposed reversible multiplier circuits are tested for Stuck-at faults (SAF) and missing gate faults (MGF) based on signature analysis.Eigen values and vectors computations on VIRTEX-5 FPGA platform cyclic Jacobi's algorithm using systolic array architecture
http://dl-live.theiet.org/content/conferences/10.1049/ic.2011.0044
The parallel iterative algorithms are the major advancements in the field of computing. These algorithms lead to efficient usage of hardware as well as obtaining faster results. In this paper, we describe architecture to compute eigen values and eigen vectors of a matrix having dimensions up to 50 × 50 using cyclic Jacobi's Algorithm. Systolic array architecture is used to apply it to matrices of larger dimensions. We have implemented the architecture on FPGA Vertex-5 that takes about 8059 LUT slices out of 69120 slices for matrices of dimensions 50 × 50.Secure scan design with isomorphic registers
http://dl-live.theiet.org/content/conferences/10.1049/ic.2011.0052
In this paper, we first introduce Isomorphic Redundancy concept. Two functionally equivalent shift registers can be Isomorphic to each other. They can be equivalent to each other by simple permutation of states m state tables. Two Isomorphically redundant circuits can be used to prevent two bit change insertion attack. In, addition we also propose a new model with the help of functionally equivalent shift registers. It is highly non-linear and scan-secure model.Design and implementation of efficient multiplier using Vedic mathematics
http://dl-live.theiet.org/content/conferences/10.1049/ic.2011.0071
Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate(MAC) and inner product are among some of the frequently used computation Intensive Arithmetic Functions(CIAF) currently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors m its arithmetic and logic unit. Since multiplication dominates the execution tune of most DSP algorithms, so there is a need of high speed multiplier. Currently, multiplication time is still the dominant factor in determining the instruction cycle time of a DSP chip. The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications . One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier. Employing this technique in the computation algorithms will reduce the complexity, execution time, power etc. This vedic based multiplier is compared with binary multiplier(partial products method).A spatial hierarchy FPGA implementation with DPR square root partitions
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0904
The customized hardware platform for spatial hierarchy construction with DPR square root partitions is validly obtained. Specialized process structures and storage structures are constructed to ensure the reutilization of presorting results on each level. The objective functions for division evaluation oriented to specific applications are scheduled. DPR partitions are built to meet intensive square root finding requests. After optimizations for algorithm and architecture, such achievement provides the starting points for future development.Low power synchronous counter using improvised conditional capture flip-flop
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0429
An 8 bit synchronous counter is designed using the improvised Clock Gated Conditional Capture Flip-Flop (CGCCFF). The Conditional Capture Flip-Flop (CCFF) outputs the data, only when the input differs from the output. But, it has redundant transitions due to continuous clock flow irrespective of the input and output logic levels. The clock gating allows the clock, only when there is a need for change in output due to a change in the input. Using, the improvised CGCCFF and hence, avoiding the redundant transitions, we observe a power saving of up to 75% compared to the conventional CCFF. Moreover, it achieves a 60% higher performance than the CCFF and a better negative setup time. Hence, we implement an 8 bit synchronous counter using the CGCC flip flop. From the experimental results, we observe that, the 8 synchronous counter with CGCCFF saves 15% power than conventional CCFF counter. We simulated the results using HSPICE in 0.18μm technology.Implementation of extended Kalman filter on FPGA
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0803
The purpose of this paper is to explore the concepts and consequences of implementing the Extended Kalman Filter (EKF) on the FPGA. The methods of Runge-Kutta and Taylor-Heun are applied to approximate the continuous time update. The methods of Rugge-Kutta and Gauss-Legendre are used to solve the Riccati equation in order to update the discrete time measurement. The simulation on Matlab Simulink and implementation on the hardware in-loop are completed. Tradeoff between clock frequency, hardware resources and design accuracy are analyzed in the design. Recommended works describe the limitation of the design and give the suggestion on how to save the hardware resources and increase the accuracy.Design and implementation of IEEE 802.16 baseband system on FPGA
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0794
In this paper, a physical-layer baseband modem is discussed based on IEEE 802.16 protocol. It is implemented on Xilinx FPGA and tested correctly in loop-mode. After channel coding, a bit stream goes through constellation mapper, pilot inserting, OFDM(Orthogonal Frequency Division Multiplexing) modulation, PAPR(Peak to Average Power Ratio) reduction and framing module to become 7 symbols in IQ parallel form prepared for RF(Radio Frequency) front end. On condition of loop-mode, these symbols become back to serial bit stream via synchronization, channel estimation, OFDM demodulation, pilot removing and constellation demapper in receiver part. In practice, the entire loop-mode system takes about 120us when clock rate is 40Mhz. As a consequence, the baseband system delay is much lower in order to satisfy the demands for high rate data processing in broadband communication.An independent FPGA implementation of graphical spatial hierarchy
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0323
The customized hardware platform for spatial hierarchy construction are validly obtained Mutual channels oriented to outward manipulations are established in FPGA speedup architecture for spatial hierarchical index structures Instance parameter adjusting mechanism are scheduled and constructed in the main stem of system. Multiple facilities for process and storage are built for the presorting operations. Specialized process structures and storage structures are constructed to ensure the reutilization of presorting results on each level. The objective functions for division evaluation oriented to specific applications are scheduled. Through evaluation and concatenation for the memory accessing sequences, optimized executing strategies are generated reliably to broaden the bandwidths of accessing channels. After optimizations for algorithm and architecture, such achievement provides the starting points for future development. (6 pages)The driver design and implementation of NAND flash based on memory technology device
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0797
With the rapid development of digital technology, the application of embedded system is more and more extensive. The demand for NAND Flash storage device is growing rapidly, but the different types of embedded equipment provided by different manufacturers do not have consistent standard. So it is very important to develop the driver of NAND Flash of specific manufacturer. In this paper, the Samsung's K9G8G08U0M chip is used as an example. The fundamental structure and operational principle of NAND Flash are introduced. And then the development process of NAND Flash driver based on Memory Technology Device (MTD) is discussed in detail. The driver development process and method are very valuable for NAND flash driver of embedded equipment.A comprehensive FPGA implementation of collision detection
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0905
The customized hardware platform for collision detection is validly obtained. The components within system are spatial hierarchy constructing block, overlapping test module with pre-projection, pre- masking module for inter-objects collision detection invalidity, parameterized traversing block between geometry elements, graphical processing system on GPU platform and finally optimization block for memory accessing.. Specialized process structures and storage structures are constructed to ensure the stable operation of collision detection system.Future of computer hardware
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0007
Summary form only given. "Experienced prophets concerning the future." are careful with predictions With this statement in mind, in this paper recent developments in computer hardware are considered along their technical possibilities and limitations. Beyond available standard multicore CPU hardware, this involves the recent impact of specialized accelerator hardware: Currently, general purpose graphic processing units (GPGPUs) and programmable specialized hardware such as FPGA processors or e.g. IBM's Cell processor are successfully used in the field of high-performance computing. This specialized co processor technology gives rise to hybrid-type processors integrating CPU and GPUs. Upcoming candidates for such hybrid-architectures are Intel's "SandyBridge" processor architecture arising from the "Larabee" project, the upcoming systems from AMD including the graphics accelerator technology of ATI Technologies into their CPUS or the future fusion processors recently announced by the companies ARM and NVIDIA under project codename "Denver". The data-level parallelism required for these architecture to achieve suitable high-performance levels has an impact on the development and use of computational electromagnetics (CEM) algorithms and simulation tools: The required use of Single Instruction Multiple Thread (SIMT) operations on massively parallel compute-kernel structures results in a severe performance sensitivity with respect to a controlled flow of the data streams. As a result, these specialized computer architectures will favour numerical schemes which implicitly support these features. High data locality and an intrinsic parallelism usually results in a good ratio between the computational workload for the floating point units (FPUs) and the need for data movement. This can be found e.g. in higher order Discontinuous Galerkin FEM time domain formulations. More generally, discretized field formulations using explicit time integration schemes commonly are easier to parallelize than those based implicit schemes, where complicated solution schemes are required for the algebraic systems of equations involved. Beyond the currently valid paradigm of massive parallelism which follows several decades of a steady increase in the average wall-clock speed of CPU architectures, current research on computational architectures also focuses on reconfigurable systems. First systems using hybrid-core computing by CPUs with programmable FPGAs are becoming available and are already in use for data intensive applications. Future systems featuring fully reconfigurable special-purpose cores that are capable to adapt to the computational task at hand are currently under development. The possible full impact of such reconfigurable core systems to the field of computational electromagnetics is yet an open subject to speculation, although some research results on FDTD implementations hard-coded on FPGAs have been published already in the past recent years. Another important topic to be addressed with future computer hardware is the need to optimize the ratio of computational performance in relation to the electric power consumption (Flop per Watt): On a technical system level, a high electric power density is cause for concern because of resulting thermal stresses and often results in the need for expensive cooling measures. On a macroscopic economical level, the costs of the electric energy consumption of the computer system itself and its external cooling systems result in increasing total costs of ownership (TCO). With an increasing need for very large scale CEM computations e.g. in computational electromagnetic compatibility testing, these TCO costs are no longer negligible even for medium scale compute-clusters in an industrial or research environment. In addition, the reduction of electric energy consumption of the compute cores is an essential technical necessity in the design of future high-performance computer systems in the exa-flop scale. With these future super computers to be available approximately in 2018 (following Moore's law) the contemporary peta-flop super computers are to be exceeded in terms of computational performance by three orders magnitude, but they may not so exceed these in terms of electric energy consumption.A FPGA ray tracing scheme with memory optimization facility
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0903
This article presents a ray tracing acceleration system realized on FPGA platform. Additionally we make improvement to the memory accessing performance and achieve ideal ratio of performance against resources. Such work will gain ray tracing more applicable regions. The global scheme includes spatial indexing hierarchy module, ray generation module, pre-masking module, packet traversal module, arithmetic module and memory optimization facility which is described specially in this article..A novel FPGA platform for ray tracing acceleration
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0322
This article presents a ray tracing acceleration system realized on FPGA platform, which fully utilizes the chip's potential under limited resources. Additionally we make global or local improvement to the architecture and algorithm, and achieve ideal ratio of performance against resources while insuring reliable operation. Such work will gain ray tracing more applicable regions as well as appraisals in theory and practice. The improving scheme includes acceleration module which creates spatial indexing hierarchy, parameterized ray generation module, premasking module, parameterized packet traversal module, arithmetic module and vector module. (6 pages)A low power multiplier architecture based on bypassing technique for digital filter
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0432
The objective of the paper is to present a low power 4×4 digital multiplier design to reduce power consumption of digital multiplier based on 2-dimensional bypassing method. Design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. The proposed bypass cells constitute the multiplier skip redundant signal transitions when the horizontally partial product or the vertical operand is zero. Hence, it is a 2-dimensional bypassing architecture using which we designed a Digital filter for low power dissipation in signal processing applications. Thorough post-layout simulations show that the power dissipation of the proposed 2D multiplier and FIR filter design based on 2D multiplier is reduced by more than 75% compared to the prior design with obscure cost of delay and area.Designed and implemented of graphics rasterization algorithm with FPGA
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0902
The rasterization stage, which is an important part of a graphics processing unit, always requires huge operations and is the bottleneck of the performance, especially for mobile devices. In this paper, the authors research the rasterization algorithm and optimize some rasterization algorithm. In the last, the authors implement a simple rasterization engine with small hardware resource of FPGA.FPGA implementation of hot spot detection in infrared video
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0518
This paper describes a Hardware Description Language (HDL) based fully customizable module for real-time Infrared (IR) hot spot detection and feature extraction from a video stream. The aim of the research was to investigate and evaluate possible solutions for object detection using connected component labelling that could be implemented within a streaming video embedded processing platform as a hardware accelerator. The proposed algorithm is based on a single-pass approach; this guarantees real-time processing together with very low resource utilisation. The hardware implementation was verified on a Xilinx XUP V2P (XC2VP30 FPGA) development board with an IR camera module interfaced as a real-time video source. The system was tested with an image resolution of 640 × 480 processing input data at a speed of 30fps which was limited by the bandwidth of the camera.The impact of neural model resolution on hardware spiking neural network behaviour
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0515
This paper contributes to the development of the proposed EMBRACE mixed-signal, reconfigurable, Network-on-Chip based hardware Spiking Neural Network. EMBRACE-FPGA is an FPGA-based prototype of the proposed EMBRACE architecture. Results from successful evolution of an EMBRACE-FPGA SNN robotics controller are presented. Noise in best fitness plots for a range of evolved EMBRACE-FPGA based SNN applications, including the robotics controller, have been observed. This paper investigates the sources of neural noise, and considers their impact in evolving digital-based hardware SNNs. The paper considers the expected performance benefits of the EMBRACE analogue neural cell.Experimental demonstration of optical processor-memory interconnection
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0755
In this work, we experimentally demonstrated the feasibility and performance of an optically-connected processor-memory system. An emulated CPU with the on-chip memory controller was implemented on a high-speed FPGA evaluation board, which communicated with another SRAM module through independent Rocket IO transceivers connected by a 2.5 Gb/s optical channel. Data integrity and error-free performance are verified with a sequence of SRAM write and read operations.FPGA based high accuracy optical flow algorithm
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0497
Motion estimation of a scene is an interesting problem in computer vision since it is the basis for the dynamic analysis of a scene. However this task is computationally intensive for conventional processors. In this work, an FPGA-based hardware architecture for real-time motion estimation is proposed. The algorithm implemented in hardware is a gradient based inverse finite element method for optical flow computation. It manages the motion estimation of the image by calculating the Gradient, Laplacian, and Velocities of each pixel in a parallel design which improves computational speed. The algorithm used in this paper has been benchmarked against many of the well known algorithms and shows superior performance in terms of average angular error and standard deviation. The FPGA design is presented with preliminary results and discussed.Design and implementation of a SoC-based security coprocessor and program protection mechanism for WSN
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.1044
The practical applications of wireless sensor networks in vulnerable areas require the communication data of sensor devices confidentiality, integrity and freshness. Furthermore the program data of sensor devices need to be protected. In this paper, we present the design, implementation and simulation of an effective hardware security coprocessor namely RC5-FKM and program protection mechanism based on system on chip (SoC) technology for wireless sensor networks (WSN). Compared with existing works, the unique features of our design includes: (1) a design of fingerprint based key management (FKM) is implemented in SoC, which is used to build secret keys for cryptographic coprocessor. (2) A program protection mechanism is proposed to prevent the program data from being read out by system intruders so as to improve the security of program data in sensor device. (3) A reusable optimized logic cell (ROTL) including some adders and registers is implemented in RC5-FKM, which results in the elimination or minimization of the additional hardware overhead. The design is mapped on FPGA and ASIC design. Results show that the hardware overhead of our design is 9.6% less than previous designs and the execution time of our hardware design is only 0.2% of that of general processors and shorter than other AES coprocessors.VHDL guidance for safe and certifiable FPGA design
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0832
Field Programmable Gate Arrays (FPGAs) are becoming increasingly popular for use within high integrity and safety critical systems. One commonly used coding language for their configuration is the VHSIC Hardware Description Language (VHDL). Whilst VHDL is used for hardware description, it is developed in a similar way to traditional software, and many safety critical software certification standards require the use of coding subsets and style guidance in order to ensure known language vulnerabilities are avoided. At present there is no recognized, public domain guidance for VHDL. This paper draws together many different sources to provide a starting discussion for a VHDL subset. (6 pages)A configurable FFT Processor
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0662
In this paper, a configurable FFT processor is presented which can be configured as 8192 point, 4096 point, 2048 point and 1024 point FFT processor. The processor is based on mixed radix algorithm and single-path delay feedback(SDF) architecture is adopted. The configurable architecture is achieved by connecting or bypassing specific processing elements. To improve processor performance, a dynamic scaling approach is adopted and internal data is formatted as self-defined floating point, and the arithmetic for the self-defined floating point is simple. The experiment results show that the approach can achieve high and constant SNR. The processor is implemented on FPGA.A hardware wrapper for the SHA-3 hash algorithms
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0478
The second round of the NIST public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). Computational efficiency of the algorithms in hardware is to be addressed during the second round of the contest. For software implementations NIST specifies an application programming interface (API) along with reference implementation for each of the designs, thereby enabling quick and easy comparison and testing on software platforms, however no such specification was given for hardware analysis. In this paper we present a hardware wrapper interface which attempts to encompass all the competition entries (and indeed, hash algorithms in general) across any number of both FPGA and ASIC hardware platforms. This interface comprises communications and padding, and attempts to standardise the hashing algorithms to allow accurate and fair area, timing and power measurement between the different designs.Synthesis of glue logic, transactors, multiplexors and serialisors from protocol specifications
http://dl-live.theiet.org/content/conferences/10.1049/ic.2010.0148
Today's system-on-chip (SoC) systems must be designed as quickly as possible by integrating IP blocks from diverse suppliers. In this paper, we present a new automata based algorithm that automatically synthesizes glue logic for SoC fabrication and Transaction-level modelling (TLM) transactors for SoC modelling. Our approach introduces a new encoding for state variables which captures data conservation property and supports simple point-to-point connections as well as those the perform functions such as multiplexing, filtering and serialising.Sliding mode observation of capacitor voltage in multilevel power converters
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0014
In this paper a sliding mode observer is designed and applied to a two-port multi-cellular power converter topology in order to observe the DC-link capacitor voltages. Among different sliding mode observers, the Sliding Mode Observer (SMO) using equivalent control approach has been selected for use because of its robustness against uncertainties in system equations. Simulation is carried out using SABER software. For practical results the controller is implemented on a TMS320C6713 DSP and two ACTEL FPGAs. The observer equations are implemented on an FPGA using a fixed-point system programmed in VHDL. (6 pages)Tiny-π: a novel formal method for specification. Analysis, and verification of dynamic partial reconfiguration processes
http://dl-live.theiet.org/content/conferences/10.1049/ic.2010.0134
On FPGA-platforms, the feature of dynamic partial reconfiguration offers a wide range of applications. We propose a new formal method for design, analysis, and verification of the reconfiguration process on such devices. The π-calculus, also known as the calculus of mobile processes, is a type of process algebra typically used to describe dynamic communicating processes. We propose the π-calculus as a foundation to model dynamic partial reconfiguration of hardware modules. A subset of this calculus that we call tiny-π can be executed in resource restricted, embedded environments which feature reconfiguration properties. As a proof-of-concept, we present a small virtual machine implementation for tiny-π. We have also implemented a compilation flow from a textual description of tiny-π specifications into executable bytecode. The virtual machine, running on an embedded Microblaze processor on an FPGA, can execute the bytecode and trigger corresponding reconfiguration commands for a dynamically reconflgurable FPGA platform.An evolvable NoC-based spiking neural network architecture
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.1732
Nature employs bio-inspired concepts such as evolution and learning to develop complex and intelligent organisms, capable of adaptation and fault tolerance. Brain-inspired paradigms such as Spiking Neural Networks (SNNs) offer the potential of elegant, low-power and robust methods of performing computing. Previous work by the authors reports a reconfigurable mixed signal Network on Chip (NoC)-based SNN architecture, with reconfigurable analogue neuron cell and digital NoC The SNN architecture includes an array of neural tiles, each incorporating a NoC router for packet-based neuron interconnect. This paper presents a Genetic Algorithm (GA) based evolution framework which interacts with the SNN architecture to evolve SNN-based solutions to problems. Simulation results are presented which verify the adaptability of the reconfigurable NoC-based SNN architecture in evolving a solution for the XOR benchmark problem. Results on the synthesised neural tile area utilisation for FPGAs are also presented. This work contributes to the realisation of a large scale reconfigurable mixed signal hardware platform for SNNs. (6 pages)The MOD procurement guidance on software safety assurance assessing and understanding software evidence
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.1547
The UK Ministry of Defence (MOD) has compiled acquisition guidance for the safety of systems containing complex electronic elements (CEEs) to complement Def Stan 00-56 Issue 4. The term CEE is defined in the Def Stan and refers to both software and custom hardware, this means that terms such as firmware become redundant from a standards perspective. CEE also encompasses the development processes of Field Programmable Gate Arrays (FPGAs) which are treated the same as software. The MOD Guidance is applicable to any acquisition project whose CEE has any effect on the safety of the overall system. This paper outlines the strategy and key points of the Guidance. Throughout the paper the term CEE and software are interchanged as they are viewed, from a safety and standards perspective, as the same problem. (12 pages)Implementation of two dimensional pulse compression based on embedded processor in FPGA
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.0131
This paper first analyses the technology characteristic of FPGA. An efficient two dimensional pulse compression processing system in which FPGA is the platform of signal processing and its embedded processor MicroBlaze is control kernel is designed and implemented using Xilinx's XC2V6000FPGA. In the limit of resource in FPGA, two different implementation architectures of pulse compression are presented in terms of speed and area restrictions. A DDR SDRAM controller which is realized in FPGA carries out efficient matrix transposition processing under the way of matrix partition linear mapping. Further more, a simple SAR imaging processing is simulated in this FPGA system for validation. (4 pages)Iris image quality assessment based on FPGA coprocessor
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.2013
The quality of iris image is a key point to affect the accuracy of iris recognition system. There are four main abnormities of captured iris image: defocus, motion blur, eyelid occlusion and eyelash occlusion. They can be distinguished by comparing different frequency components of the image. This paper describes a technique of using Field Programmable Gate Arrays (FPGA) coprocessor to assess the quality of the iris image in a Texas Instrument (TI) Digital Signal Processor (DSP) based Iris Recognition System, by implementing Laplacian Sharpening and 2D-FET transform on the chip. FPGA has become an extremely cost-effective mean of computing algorithms to improve system performance and enhance the computation capability and flexibility of the iris recognition system based on DSP.Realization on the demonstration platform of multi-form standard video source
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.1897
Presently, the digital video technique is applied widely more and more in people life. This paper realizes the general platform based on the Virtex-5 FPGA. Through video daughter card, it can process some kinds of analog input video, such as composite, S-Video, component. By use of timing control module, simple de-interlacing module and color space conversion module, and so on, PAL and NTSC standard video can all display clearly. This establishes a foundation for HD video post processing research.Design of DDR2 SDRAM controller for video post processing pipeline
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.1904
To satisfy real-time high-definition video processing requirement of video post processing pipeline, this paper proposes a novel DDR2 controller design which efficiently and selectively integrates the DDR2 SDRAM controller created by Xilinx MIG (Memory Interface Generator) and the control module of MPMC (Multi-Port Memory Controller) . The DDR2 controller is implemented as a part of the whole pipeline of a video post processing processor which has been verified in the Xilinx XUP5 Lxt-110t FPGA. Many experimental results have shown that this DDR2 controller demonstrates properties of low-latency, highthroughout, high bus utilization compared to the individual MIG and MPMC controllers, and meets the real-time HD processing requirements for this video post processing processor.Research on pipeline R2<sup xmlns="http://pub2web.metastore.ingenta.com/ns/">2</sup>SDF FFT
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.0174
The resource utilization of butterflies, multipliers, memory size, and control logic was analyzed according to several pipeline FFT processors. Radix-2<sup xmlns="http://pub2web.metastore.ingenta.com/ns/">2</sup> Single-path Delay Feedback (R2<sup xmlns="http://pub2web.metastore.ingenta.com/ns/">2</sup>SDF) was proposed due to the limit of hardware resource and real-time in ASIC design; gave the scheme, pipeline architecture, flow of BFI and BFII; did Signal to Quantization Noise Ratio (SQNR) simulation for various bit-widths, round or cut off deal per stage, different input/output word lengths; implemented in Xilinx series FPGA V4SX55 with VHDL, did pulse compression in one radar project to verify R2<sup xmlns="http://pub2web.metastore.ingenta.com/ns/">2</sup>SDF algorithm; R2<sup xmlns="http://pub2web.metastore.ingenta.com/ns/">2</sup>SDF FFT need the least resource, has high real-time performance, is suitable for VLSI implementation. (5 pages)FPGA implementation of new real-time image encryption based switching chaotic systems
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.1733
Chaos-based encryption has suggested a new and efficient way to deal with the problem of fast and highly secure image encryption. In this paper, a new chaotic key generator for image encryption and its FPGA implementation based on a chaos switching rule between Lorenz's and Lm's non-linear systems is proposed for designing a real-time secure symmetric encryption scheme. The originality of this new scheme is that it allows a low cost image encryption for embedded systems while still providing a good trade-off between performance and hardware resources. Our experimental results have demonstrated the feasibility and the efficiency of our secure solution on Xilinx FPGA virtex technology. Thorough experimental tests are carried out with detailed analysis, demonstrating the high security and fast encryption speed of the new scheme while still able to resist statistical and Key analysis attacks. (6 pages)Hybrid access agent design in large scale COTS based radar parallel processing system
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.0456
This paper focuses on resource access issue for the large scale COTS based radar processing systems. Since designing and deployment of an agent in processing system is the commonly accepted approach, several major agent schemes are inspected and discussed in detail. Then we reach the point that a hybrid agent architecture is more feasible in large scale radar processing systems. At the end of the paper, a COTS based practical hybrid agent solution is provided and proved to be scalable and effective. (4 pages)A remote medical monitoring system based on GSM network
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.1970
This paper presents a remote medical monitoring system based on GSM (Global System for Mobile communications) network. It is a kind of family medical network system. Firstly, the system structure of the monitoring system is proposed, and then the design of each module is introduced. This system takes advantage of the powerful GSM network to implement remote communication in the form of short messages and uses FPGA as the control center to realize the family medical monitoring network.Dynamic reconfigurable storage and pretreatment system of SAR signal processing using Nios II architecture
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.0424
Because of synthetic aperture radar (SAR) is a powerful remote sensing technique, there has been growing interest in using SAR to obtain high resolution image. Modern high- performance SAR requires advanced and sophisticated signal processing technique to get high-quality image products. Meanwhile, the semiconductor technologies are updated day after day, programmability and flexibility are the trend of current electronic system, and it leads to the advent of system-on-chip (SOC). The Nios II, a soft-core processor integrated in Altera FPGA chip, is characterized by its flexibility and programmability. In this paper, a dynamic reconfigurable storage and pretreatment system of SAR signal processing is designed and realized based on the Nios II soft-core processor. The proposed architecture takes advantage of the embedded CPU to control all the peripherals, highly increased the efficiency of the design. (4 pages)Data wordlength reduction in 90 nm multipliers
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.1723
Digital signal processing applications need complex arithmetic functions for implementing filters and real time statistical operations. Power consumption in these systems directly relies on their multipliers precision, as a bigger bitwidth will result in higher active power figures. On the other hand, the resolution of the signal processing block also relies on the multiplier precision, where lowering the bitwidth will result in less accuracy. This dilemma becomes specially problematic in portable devices where the optimum equilibrium needs to be found in order to get acceptable results with the longest possible battery life. An ASIC based configurable approach where the multiplier bitwidth can be modified at runtime is presented in this paper. It allows the accuracy of the output to be dynamically reduced or extended, in order to get power-related benefits, as the dynamic power consumption can be optimized to the application needs. This paper presents new results on applying this technique to a Wallace tree-based multiplier synthesized in 90 nm using standard cell libraries. (6 pages)Xilinx Virtex-5 FPGA based video input and output interface design
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.1899
In this paper, based on the Xilinx Virtex-5 FPGA, a video input and output interface circuitry including a video input daughter-card, a simple de-interlacing module, a YCrCb to RGB color space conversion module and a video output interface are designed. This System constitutes a basic infrastructure for our HD video post processing processor which is under development.Suitability of FPGA for computationally intensive image processing algorithms
http://dl-live.theiet.org/content/conferences/10.1049/ic.2009.0175
Modern age multimedia devices involve lot of multimedia tasks like image, video or speech processing. In order to meet the need of these complex multimedia tasks, efficient and high performance image processing systems need to be designed in a short time schedule. Existing platforms for image processing hardly serve the requirements of these realtime image processing tasks. The hardware platforms have emerged as the most viable solution for improving the performance of such image processing systems. The introduction of reconfigurable devices and system level hardware programming languages has further accelerated the hardware design of image processing systems. In this paper, we have explored the features of field programmable gate array, which improve the performance of complex image processing algorithms. Also, the results of point-based & window-based image processing algorithms implemented in MATLAB and VHDL are compared. (3 pages)New design methodologies & synthesis techniques for complex FPGA designs
http://dl-live.theiet.org/content/conferences/10.1049/ic_20080615
With diverse applications for FPGAs in the automotive, consumer, military/aerospace, networking, medical or wireless markets - designers are faced with an equally diverse set of implementation challenges. FPGA designs may have aggressive performance and area objectives or stringent operational requirements for safety-critical applications. Logic synthesis is among the most critical steps in ensuring these design goals are met within the required market window. In this this session you will learn how advances in FPGA synthesis have kept pace with the latest device architectures. Among the topics to be discussed are latest innovations in physical synthesis, design analysis, synthesis for operational safety, and incremental design flows. (19 pages)Verification algorithm of a sequential circuit's equivalence based on state transfer graph
http://dl-live.theiet.org/content/conferences/10.1049/ic_20080296
An equivalence verification algorithm of sequential circuits based on state transfer graph (STG) is presented in this paper, which obtains some certain useful information through verifying the corresponding state transfer graphs' isomorphism, namely that two corresponding sequential circuits' equivalence . And the verifying includes two steps: firstly, find out all state pairs of the vertexes, which are being verified; secondly verify the equivalence of state pairs, if all the state pairs can be matched as equal state pairs, thus we can come to a conclusion that the corresponding circuits have the same sequential behavior. The algorithm mainly verifies ISCAS85 circuits and some simple state transfer graphs, and the final experiment data shows that the algorithm introduced in the paper will obtain better results compared to BDD(binary decision diagram) and SET(symbolic trajectory evaluation) methods.Benefits and pitfalls of building and buying-in: choosing chips and boards
http://dl-live.theiet.org/content/conferences/10.1049/ic_20080610
Benefits and pitfalls of building and buying-in: choosing chips and boards programmable devices of all types provide users with the fundamental ability to quickly try out their ideas and interactively develop their designs. Well that's the theory, but in practice many are slow to make progress due to the physical issues associated with modern device packaging. This session considers how useful it is to exploit prefabricated boards and considers not only the obvious advantages of buying in boards but also the pitfalls and challenges of using such boards for education, device evaluation, design development and on into production. An ever growing number of FPGA users do not have a traditional hardware engineering background; could this drive demand for boards to a new level? (13 pages)Developing analytical techniques for FPGA architecture design
http://dl-live.theiet.org/content/conferences/10.1049/ic_20080612
This talk will highlight some of the key issues in designing programmable systems, as seen from the academic perspective. The challenges involved in the development of new architectures will be outlined. We will focus on the use of analytical and model-based techniques and their role in guiding architecture design processes. In particular, we will emphasise the deployment of these techniques for modern heterogeneous FPGAs. (18 pages)Designing heterogeneous systems including programmable hardware, multicore processors, DSP, processors and more
http://dl-live.theiet.org/content/conferences/10.1049/ic_20080616
Designers working with programmable hardware can choose from a wide selection of platforms including off-the-shelf, custom or application-specific, field-programmable, configurable and many other products and devices. The range of options and distinct application requirements is growing and designers have to understand and distinguish between the options available to them. In this talk, Chris draws upon his wide-ranging knowledge of the semiconductor industry, differing application markets ranging from consumer to defence and experience from Cambridge Consultants' projects to offer some insight into the platform choices available; how they may be differentiated and how an investment in them might be protected given the level of engineering development and product life-cycle challenges that must be met. Further observations offered regarding market trends, choice of computation model, program memory system, development and verification tools and sourcing underlying intellectual property. (27 pages)Study and discussion about college bilingual teaching - teaching reform and practice of the course "Principles and Application of Programmable Devices"
http://dl-live.theiet.org/content/conferences/10.1049/ic_20080287
Education toward modernization, the world and the future, this is a requirement for the development of education in our country. The internationalization influences China's higher education increasingly and has become one of the most important standards of school level. The introducing of bilingual teaching in colleges and universities is the need for training excellent and internationally competitive people. Combined with the teaching reform and practice of the course "Principles and Application of Programmable Devices", this paper analyzes textbook choosing, teaching methods and teaching effectiveness in bilingual teaching. And finally the reform of bilingual education is further studied and discussed.Exploiting the SoC capability of high performance FPGAs - a video case study
http://dl-live.theiet.org/content/conferences/10.1049/ic_20080613
As high performance applications become increasingly complex, reconfigurable computing must evolve to address the industry's shifting needs. Multi-layered FPGA SoC platforms can enable rapid system development and provide the designer with control over their own differentiating IP. This presentation will describe the key challenges faced by today's video system designers and how FPGA technologies can deliver both fast time to market and high performance processing. Specifically, a video framework is described targeting representative multi-stream video processing applications. (24 pages)Performance evaluation of VHDL coding techniques for optimized implementation of IEEE 802.3 transmitter
http://dl-live.theiet.org/content/conferences/10.1049/cp_20080199
This paper is focus on to implement IEEE 802.3 MAC transmitter using different VHDL coding techniques. We propose consequences of VHDL coding styles on area utilization and speed. Optimization for maximum speed can be achieved by FSM based approach. While targeting higher speed device area utilization is severely affected. To have a balance among area and speed optimization, we have explored synthesis options along with VHDL coding styles. With this approach FPGA area utilization for MAC implementation is reduced. Recognizing the importance of hardware architecture in relation to optimization of area and speed of operation, our implementation results shows that the performance depends on area constraint, speed constraint , vhdl coding style, FSM encoding styles, multiplexer , priority encoder extraction, fan out and register balancing.An optimal IEEE 1500 core wrapper design for improved test access and reduced test time
http://dl-live.theiet.org/content/conferences/10.1049/cp_20080663
IEEE 1500 test wrappers that enable higher test bandwidth capability, system bus connectivity and efficient test vector organization are presented. Embedded core wrappers and test vectors that seamlessly work with ASIC and FPGA design flows are illustrated. Implementation and test-chip design show the positive impact on test time with potential for minimal wiring and logic overhead savings.