New Publications are available for IET Circuits, Devices & Systems
http://digital-library.theiet.org/content/journals/iet-cds?TRACK=RSS
New Publications are available now online for this publication.
Please follow the links to view the publication.Volume 9, Issue 6
http://digital-library.theiet.org/content/journals/iet-cds/9/6
2015-11-01T00:00:00ZVolume 9, Issue 5
http://digital-library.theiet.org/content/journals/iet-cds/9/5
2015-09-01T00:00:00ZVolume 9, Issue 4
http://digital-library.theiet.org/content/journals/iet-cds/9/4
2015-07-01T00:00:00ZVolume 9, Issue 3
http://digital-library.theiet.org/content/journals/iet-cds/9/3
2015-05-01T00:00:00ZVolume 9, Issue 2
http://digital-library.theiet.org/content/journals/iet-cds/9/2
2015-03-01T00:00:00ZVolume 9, Issue 1
http://digital-library.theiet.org/content/journals/iet-cds/9/1
2015-01-01T00:00:00ZVolume 8, Issue 6
http://digital-library.theiet.org/content/journals/iet-cds/8/6
2014-11-01T00:00:00ZVolume 8, Issue 5
http://digital-library.theiet.org/content/journals/iet-cds/8/5
2014-09-01T00:00:00ZVolume 8, Issue 4
http://digital-library.theiet.org/content/journals/iet-cds/8/4
2014-07-01T00:00:00ZVolume 8, Issue 3
http://digital-library.theiet.org/content/journals/iet-cds/8/3
2014-05-01T00:00:00ZVolume 8, Issue 2
http://digital-library.theiet.org/content/journals/iet-cds/8/2
2014-03-01T00:00:00ZVolume 8, Issue 1
http://digital-library.theiet.org/content/journals/iet-cds/8/1
2014-01-01T00:00:00ZVolume 7, Issue 6
http://digital-library.theiet.org/content/journals/iet-cds/7/6
2013-11-01T00:00:00ZVolume 7, Issue 5
http://digital-library.theiet.org/content/journals/iet-cds/7/5
2013-09-01T00:00:00ZVolume 7, Issue 4
http://digital-library.theiet.org/content/journals/iet-cds/7/4
2013-07-01T00:00:00ZVolume 7, Issue 3
http://digital-library.theiet.org/content/journals/iet-cds/7/3
2013-05-01T00:00:00ZVolume 7, Issue 2
http://digital-library.theiet.org/content/journals/iet-cds/7/2
2013-03-01T00:00:00ZVolume 7, Issue 1
http://digital-library.theiet.org/content/journals/iet-cds/7/1
2013-01-01T00:00:00ZVolume 6, Issue 6
http://digital-library.theiet.org/content/journals/iet-cds/6/6
2012-11-01T00:00:00ZVolume 6, Issue 5
http://digital-library.theiet.org/content/journals/iet-cds/6/5
2012-09-01T00:00:00ZVolume 6, Issue 4
http://digital-library.theiet.org/content/journals/iet-cds/6/4
2012-07-01T00:00:00ZVolume 6, Issue 3
http://digital-library.theiet.org/content/journals/iet-cds/6/3
2012-05-01T00:00:00ZVolume 6, Issue 2
http://digital-library.theiet.org/content/journals/iet-cds/6/2
2012-03-01T00:00:00ZVolume 6, Issue 1
http://digital-library.theiet.org/content/journals/iet-cds/6/1
2012-01-01T00:00:00ZVolume 5, Issue 6
http://digital-library.theiet.org/content/journals/iet-cds/5/6
2011-11-01T00:00:00ZVolume 5, Issue 5
http://digital-library.theiet.org/content/journals/iet-cds/5/5
2011-09-01T00:00:00ZVolume 5, Issue 4
http://digital-library.theiet.org/content/journals/iet-cds/5/4
2011-07-01T00:00:00ZVolume 5, Issue 3
http://digital-library.theiet.org/content/journals/iet-cds/5/3
2011-05-01T00:00:00ZVolume 5, Issue 2
http://digital-library.theiet.org/content/journals/iet-cds/5/2
2011-03-01T00:00:00ZVolume 5, Issue 1
http://digital-library.theiet.org/content/journals/iet-cds/5/1
2011-01-01T00:00:00ZVolume 4, Issue 6
http://digital-library.theiet.org/content/journals/iet-cds/4/6
2010-11-01T00:00:00ZVolume 4, Issue 5
http://digital-library.theiet.org/content/journals/iet-cds/4/5
2010-09-01T00:00:00ZVolume 4, Issue 4
http://digital-library.theiet.org/content/journals/iet-cds/4/4
2010-07-01T00:00:00ZVolume 4, Issue 3
http://digital-library.theiet.org/content/journals/iet-cds/4/3
2010-05-01T00:00:00ZVolume 4, Issue 2
http://digital-library.theiet.org/content/journals/iet-cds/4/2
2010-03-01T00:00:00ZVolume 4, Issue 1
http://digital-library.theiet.org/content/journals/iet-cds/4/1
2010-01-01T00:00:00ZVolume 3, Issue 6
http://digital-library.theiet.org/content/journals/iet-cds/3/6
2009-12-01T00:00:00ZVolume 3, Issue 5
http://digital-library.theiet.org/content/journals/iet-cds/3/5
2009-10-01T00:00:00ZVolume 3, Issue 4
http://digital-library.theiet.org/content/journals/iet-cds/3/4
2009-08-01T00:00:00ZVolume 3, Issue 3
http://digital-library.theiet.org/content/journals/iet-cds/3/3
2009-06-01T00:00:00ZVolume 3, Issue 2
http://digital-library.theiet.org/content/journals/iet-cds/3/2
2009-04-01T00:00:00ZVolume 3, Issue 1
http://digital-library.theiet.org/content/journals/iet-cds/3/1
2009-02-01T00:00:00ZVolume 2, Issue 6
http://digital-library.theiet.org/content/journals/iet-cds/2/6
2008-12-01T00:00:00ZVolume 2, Issue 5
http://digital-library.theiet.org/content/journals/iet-cds/2/5
2008-10-01T00:00:00ZVolume 2, Issue 4
http://digital-library.theiet.org/content/journals/iet-cds/2/4
2008-08-01T00:00:00ZVolume 2, Issue 3
http://digital-library.theiet.org/content/journals/iet-cds/2/3
2008-06-01T00:00:00ZVolume 2, Issue 2
http://digital-library.theiet.org/content/journals/iet-cds/2/2
2008-04-01T00:00:00ZVolume 2, Issue 1
http://digital-library.theiet.org/content/journals/iet-cds/2/1
2008-02-01T00:00:00ZVolume 12, Issue 3
http://digital-library.theiet.org/content/journals/iet-cds/12/3
2018-05-01T00:00:00ZVolume 12, Issue 2
http://digital-library.theiet.org/content/journals/iet-cds/12/2
2018-03-01T00:00:00ZVolume 12, Issue 1
http://digital-library.theiet.org/content/journals/iet-cds/12/1
2018-01-01T00:00:00ZVolume 11, Issue 6
http://digital-library.theiet.org/content/journals/iet-cds/11/6
2017-11-01T00:00:00ZVolume 11, Issue 5
http://digital-library.theiet.org/content/journals/iet-cds/11/5
2017-09-01T00:00:00ZVolume 11, Issue 4
http://digital-library.theiet.org/content/journals/iet-cds/11/4
2017-07-01T00:00:00ZVolume 11, Issue 3
http://digital-library.theiet.org/content/journals/iet-cds/11/3
2017-05-01T00:00:00ZVolume 11, Issue 2
http://digital-library.theiet.org/content/journals/iet-cds/11/2
2017-03-01T00:00:00ZVolume 11, Issue 1
http://digital-library.theiet.org/content/journals/iet-cds/11/1
2017-01-01T00:00:00ZVolume 10, Issue 6
http://digital-library.theiet.org/content/journals/iet-cds/10/6
2016-11-01T00:00:00ZVolume 10, Issue 5
http://digital-library.theiet.org/content/journals/iet-cds/10/5
2016-09-01T00:00:00ZVolume 10, Issue 4
http://digital-library.theiet.org/content/journals/iet-cds/10/4
2016-07-01T00:00:00ZVolume 10, Issue 3
http://digital-library.theiet.org/content/journals/iet-cds/10/3
2016-05-01T00:00:00ZVolume 10, Issue 2
http://digital-library.theiet.org/content/journals/iet-cds/10/2
2016-03-01T00:00:00ZVolume 10, Issue 1
http://digital-library.theiet.org/content/journals/iet-cds/10/1
2016-01-01T00:00:00ZVolume 1, Issue 6
http://digital-library.theiet.org/content/journals/iet-cds/1/6
2007-12-01T00:00:00ZVolume 1, Issue 5
http://digital-library.theiet.org/content/journals/iet-cds/1/5
2007-10-01T00:00:00ZVolume 1, Issue 4
http://digital-library.theiet.org/content/journals/iet-cds/1/4
2007-08-01T00:00:00ZVolume 1, Issue 3
http://digital-library.theiet.org/content/journals/iet-cds/1/3
2007-06-01T00:00:00ZVolume 1, Issue 2
http://digital-library.theiet.org/content/journals/iet-cds/1/2
2007-04-01T00:00:00ZVolume 1, Issue 1
http://digital-library.theiet.org/content/journals/iet-cds/1/1
2007-02-01T00:00:00ZWindow function for fractional-order HP TiO2 non-linear memristor model
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0414
<p>In order to overcome the boundary effect and boundary lock problem existing in classical Hewlett-Packard (HP) <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mrow> <mml:mi>Ti</mml:mi> </mml:mrow> <mml:msub> <mml:mrow> <mml:mi>O</mml:mi> </mml:mrow> <mml:mn>2</mml:mn> </mml:msub> </mml:math> </script> non-linear model, the authors propose a novel window function for the fractional-order HP <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mrow> <mml:mi>Ti</mml:mi> </mml:mrow> <mml:msub> <mml:mrow> <mml:mi>O</mml:mi> </mml:mrow> <mml:mn>2</mml:mn> </mml:msub> </mml:math> </script> non-linear drift model, in which the fractional calculus is utilised to reflect the memory property of the memristor device. The novel window function is general and they can take the previously reported well-known window functions as its special cases by turning parameter <i>a</i>. Compared with the integer-order model, the order <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mi>α</mml:mi> </mml:math> </script> and <i>a</i> in the fractional-order case is important parameters to flexibly realise the non-linear dopant drift of memristor model even when a wider amplitude range of the input voltage is applied. Simulation results illustrate that their model is flexible, scalable to guarantee the state variable <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mi>x</mml:mi> <mml:mo>(</mml:mo> <mml:mi>t</mml:mi> <mml:mo>)</mml:mo> </mml:math> </script> and the memristor value <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:msub> <mml:mi>M</mml:mi> <mml:mi>α</mml:mi> </mml:msub> <mml:mo>(</mml:mo> <mml:mi>x</mml:mi> <mml:mo>)</mml:mo> </mml:math> </script> switched between the low and high levels by choosing suitable parameter <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mi>α</mml:mi> </mml:math> </script> and <i>a</i>. A simple practical application also confirms the efficiency of their model to reveal the non-linear dopant kinetics of the memristor device.</p>2018-02-02T00:00:00ZTwo-dimensional models for quantum effects on short channel electrostatics of lightly doped symmetric double-gate MOSFETs
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0046
<p>Analytical Verilog-A compatible 2D model including quantum short channel effects and confinement for the potential, threshold voltage and the carrier charge sheet density for symmetrical lightly doped double-gate metal-oxide-semiconductor field effect transistors (MOSFETs) is developed. The proposed models are not only applicable to ultra-scaled devices but they have also been derived from 2D Poisson and 1D Schrödinger equations including 2D electrostatics, in order to incorporate quantum mechanical effects. Electron and hole quasi-Fermi potential effects were considered. The models are continuous and have been verified by comparison with COMSOL and BALMOS numerical simulations for channel lengths down to 7 nm at 1 nm oxide thicknesses; very good agreement within ±5% has been observed for silicon thicknesses down to 3 nm.</p>2018-01-12T00:00:00ZTuning approach for first-order filters and new current-mode circuit example
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0431
<p>An approach of tuning first-order filters is proposed in this study. The proposed approach is based on employing feedback in first-order filter circuits, wherein a scaled output is combined with the input signal, so as to facilitate easy tuning of filter parameters. Various options of tuning the filter parameters are explored by employing feedback from low-pass, high-pass or all-pass outputs. The approach enables easy tuning of filter parameters by varying the gain of an external amplifier, without adjusting the passive elements comprising the filter core. A new current-mode filter circuit is further proposed, which employs a recently introduced active element, namely an extra-X current conveyor. The new approach is used in the designed first-order filter circuit. The new proposed circuit benefits by employing only a grounded capacitor, exhibits low-input and high-output impedances. The approach of tuning filter parameters through external means, without disturbing filter core, and the new proposed circuit are verified through simulations with promising results. As further modification to the proposed approach, the possibility of realising pole–zero symmetry is presented, which makes the new proposed tuning method useful for both existing and future designs.</p>2018-02-06T00:00:00ZSymptom reliability: S-parameters evaluation of power laterally diffused-metal–oxide–semiconductor field-effect transistor after pulsed-RF life tests for a radar application
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.0005
<p>This paper treats the <i>s</i>-parameter performance degradation by hot electron induced for N-MOSFET devices used in radar applications. This study is relevant for devices operating in the RF frequency regime. The power LD-MOSFET device (0.8 µm channel length, Gate oxide thickness 0.065 µm and 2.2 GHz) are designed and fabricated. Subsequently, life tests in pulsed RF cause, after ageing, the electrical behaviour and its relation with charge trapping at the interface are presented and discussed. Unlike all other current methods, a complete evaluation of S parameters is carried out to obtain key information concerning the defects location. The <i>s</i>-parameter performance degradation can be explained by the transconductance and the miller capacitance move, and by the leakage current augmentation IG, which is shown by hot-carrier event from the Si/SiO<sub>2</sub> interface state generation and/or in a build up of negative charge. Also, the degradation can be predicted by the experimental correlation of RF and dc performance shifts, favour by the measurement of dc performance or initial leakage current. The analysis accompanied proves that the <i>s</i>-parameters shift by hot electron induced and should be taken into consideration in the design. Through physical processes of ATLAS-SILVACO simulations these degradation phenomena are located and confirmed</p>2018-03-07T00:00:00ZSoft input decoder for high-rate generalised concatenated codes
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0347
<p>Generalised concatenated (GC) codes are well suited for error correction in flash memories for high-reliability data storage. The GC codes are constructed from inner extended binary Bose–Chaudhuri–Hocquenghem (BCH) codes and outer Reed–Solomon codes. The extended BCH codes enable high-rate GC codes and low-complexity soft input decoding. This work proposes a decoder architecture for high-rate GC codes. For such codes, outer error and erasure decoding are mandatory. A pipelined decoder architecture is proposed that achieves a high data throughput with hard input decoding. In addition, a low-complexity soft input decoder is proposed. This soft decoding approach combines a bit-flipping strategy with algebraic decoding. The decoder components for the hard input decoding can be utilised which reduces the overhead for the soft input decoding. Nevertheless, the soft input decoding achieves a significant coding gain compared with hard input decoding.</p>2018-01-29T00:00:00ZRigorous mathematical model of through-silicon via capacitance
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0157
<p>Through-silicon vias (TSVs) are a key technology for three-dimensional integrated circuits. As the integration of circuits increases, high temperature has a greater effect on the performance of the TSV interconnections. The metal–oxide semiconductor (MOS) effect is one of the most important temperature-dependent characteristics of a TSV. This study introduces the mathematical model of a TSV to predict the MOS effect more accurately. The thermal effect that varies due to the change in the TSV capacitance and depletion region can be modelled by the non-linear the Poisson equation including mobile charge carriers. In procedures to solve this equation, the proposed method considers not only the thermal effect of intrinsic carrier concentration and silicon bandgap energy but also the shift effect of the flat band voltage due to the Si–SiO<sub>2</sub> interface charges. In addition, since it considers the minority carrier generation rate, which is dependent on the change of gate voltage, the MOS effect in a TSV can be explained more accurately using equations derived from these procedures. To verify the proposed mathematical model, comparison with the numerical method is carried out, and these results show that the proposed method is very accurate in explaining the MOS effect in a TSV.</p>2018-03-05T00:00:00ZReconfigurable arithmetic logic unit designed with threshold logic gates
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.0046
<p>In recent years, there is a trend towards the development of reconfigurable circuits where devices using them offer flexibility and performance. Different technologies are explored, such as threshold logic gates (TLGs), which are one of the most promising future technologies, and researchers are examining and improving different characteristics such as density, performance and power dissipation. This research presents a 4-bit arithmetic logic unit (ALU), which was designed using TLGs through reconfigurable logic blocks with a universal circuit configured with three stages based on a floating-gate metal oxide semiconductor transistor with more than one control gate, which was named neu-complementary metal oxide semiconductor (<i>ν</i>-CMOS). The main contribution is that this device is configured as a <i>ν</i>-CMOS inverter and has the ability to program the threshold voltage of its transfer curve by applying an external voltage to the additional control gates. The number of input bits and the magnitude of the weighted input capacitances related to control gates of the <i>ν</i>-CMOS inverters is obtained and analyzed by using the graphical method (floating-gate potential diagram). Finally, the proposed 4-bit ALU shows similar results as those measured from the ALUs implemented in the field programmable gate array evaluation kit and the Motorola chip MC14581B.</p>2018-05-01T00:00:00ZReal-time temperature compensation for tunable cavity-based BPFs and BSFs
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.0019
<p>In this study, a real-time temperature compensation control system for tunable high-<i>Q</i> cavity-based filters are designed, implemented, and experimentally validated. Both bandpass (BPFs) (700–1000 MHz) and bandstop filters (BSFs) (1300–1600 MHz) with high-<i>Q</i> (<script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mi>Q</mml:mi> <mml:mo>≃</mml:mo> <mml:mn>400</mml:mn> </mml:math> </script>) resonators are monitored in real time to compensate for any temperature variations. The monitoring scheme includes additional resonators that share the same tuning piezoelectric actuators with the resonators of the radio frequency (RF) filters. An oscillator is coupled with each monitoring resonator resulting in an output signal at a frequency directly linked to the RF resonance. Each monitoring resonator is controlled by a user-provided input through a closed-loop in real time. The presented system is capable of compensating for temperature variations in the <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mo>−</mml:mo> <mml:mn>40</mml:mn> </mml:math> </script> and <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:msup> <mml:mn>80</mml:mn> <mml:mo>∘</mml:mo> </mml:msup> <mml:mrow> <mml:mi>C</mml:mi> </mml:mrow> </mml:math> </script> range. The average system resolution varies from 0.23 to 9 MHz, depending on temperature, with a 1 ms sensing period. The closed-loop frequency shift is 6.5 MHz (0.93%) and 8.75 MHz (0.65%) for the BPFs and BSFs, respectively, in the <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mo>−</mml:mo> <mml:mn>40</mml:mn> </mml:math> </script> to <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:msup> <mml:mn>80</mml:mn> <mml:mo>∘</mml:mo> </mml:msup> <mml:mrow> <mml:mi>C</mml:mi> </mml:mrow> </mml:math> </script> temperature range. This is to be compared with the open-loop change of 256 MHz (36%) and 590 MHz (44%) for the same temperature change. The monitoring oscillator power leakage to the RF cavities is optimised and measured to −101 dBm.</p>2018-04-12T00:00:00ZPulse train controlled quadratic buck converter operating in discontinuous conduction mode
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0194
<p>Emerging technologies in the field of integrated circuits demand wider conversion ratios with a substantial reduction in size and weight. Quadratic buck converter is a popular choice for such an application which is investigated under voltage-mode pulse train control operating in discontinuous conduction mode. The combination of high-power control pulse <i>P</i> <sub>H</sub> and low-power control pulse <i>P</i> <sub>L</sub> in a control pulse repetition cycle which has a significant effect on the control performance of the system is studied. For a reliable design, a complete assessment of its dynamics under all possible operating conditions is essential for its safe operating horizons. Computer simulations are performed to capture the periodic transformation undergone due to border collision bifurcation. However, the stable periodic operation is examined with the supporting evidence of movement of eigenvalues from 2D discrete-time model and maximal Lyapunov exponent obtained using QR factorisation method for the variation in the input voltage and the load conditions. An experimental setup is also built to verify the system dynamics which are observed in simulations and analytical results.</p>2018-02-13T00:00:00ZPrecomputation-based radix-4 CORDIC for approximate rotations and Hough transform
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0492
<p>Vector rotation is an important component of algorithms in digital signal processing and robotics. Often, the rotation does not require very high accuracy. This study presents a lowoverhead sign-precomputation-based architecture for approximate rotation using the coordinate rotation digital computer (CORDIC) algorithm. The proposed architecture is independent of <i>Z</i>-datapath, and involves precomputation of the direction of rotation for each micro-rotation angle. The approach involves selecting the optimal micro-rotation angles from a set of elementary angles in run time. Careful selection and elimination of the redundant micro-rotation angles leads to a maximum of three iterations for a majority of the input angles while also simultaneously reaching within 0:45 (of the desired rotation angle). An field programmable gate array (FPGA) implementation of the proposed rotation mode CORDIC on XC7K70T-3FBG676 Kintex-7 using Xilinx ISE 13.2 achieves roughly 50% reduction in slice-delay product and power-delay product compared to recent designs. An application of approximate rotation to Hough transform-based lane detection is presented. An efficient algorithm for generation of vote addresses in the parameter space is proposed. It is shown that accurate lane detection is possible along with resource savings using the proposed CORDIC. The proposed architecture reduces the number of additions roughly by a factor of 20 compared with the conventional method of computing a parameter for each feature point.</p>2018-01-31T00:00:00ZPrecision analysis with analytical bit-width optimization process for linear circuits with feedbacks
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0514
2018-03-06T00:00:00ZPipelined Decoder for the Limited Context Order Burrows-Wheeler-Transformation
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0496
2018-04-20T00:00:00ZPerformance Study of Optical Resonator based Filter Architectures
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.0087
2018-04-18T00:00:00ZOscillation analysis and current peak reduction in paralleled SiC MOSFETs
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0255
<p>Parallel connection of power metal oxide semiconductor field effect transistors (MOSFETs) is often used in the high current side of power conversion systems to obtain a thermal dispersion and low conduction losses. However, a parallel connection may lead to a current unbalance due to the difference of parasitic parameters and switching characteristics of the paralleled devices. The current unbalance generates current oscillations, and in the worst case, it may lead to complete destruction of the power devices. This study analyses an inherent oscillation of two paralleled SiC MOSFETs, under current unbalance conditions. Based on the proposed analysis, it is found that the parasitic inductance is the main cause of the coupled oscillation, which is composed of two different oscillation frequencies. In this study, the coupled oscillation leads to a difference of peak currents between paralleled devices. The circuit conditions, considering the parasitic inductances, are investigated to suppress the coupled oscillation. As a result, a reduction of the common parasitic inductance allows preventing the coupled oscillation and to suppress the peak combined current of paralleled devices. Moreover, a peak current reduction by 37.8% can be achieved, as a result of eliminating the coupled oscillation.</p>2018-01-30T00:00:00ZOptimal design of wideband fractional order digital integrator using symbiotic organisms search algorithm
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0162
<p>Optimal design of digital rational approximations with <i>α</i>-dependant coefficients to model the fractional order integrator of any arbitrary order <i>α</i>, where <i>α</i> ε (0, 1), is presented in this work. The analytical expressions of the coefficients for the proposed fractional order digital integrators (FODIs) are derived by a two-step method: (a) the coefficients of FODIs for <i>α</i> varying from 0.01 to 0.99 in steps of 0.01 are determined by a meta-heuristic optimisation algorithm called symbiotic organisms search (SOS) and (b) curve fitting is applied on the SOS-optimised coefficients to obtain their generalised expressions. Previous works dealing with the design of FODI based on various meta-heuristic optimisers have considered only a few specific fractional orders; hence, the practical usability of such designs is restricted. This gap provides the motivation for conducting this research. Design quality robustness and convergence consistency of SOS are extensively compared with three other well-known meta-heuristic algorithms. The superior modelling accuracy of the proposed designs is justified by comparing with the recent literature. Simulation results validate the effectiveness of the proposed models as a fractional order proportional–integral controller.</p>2018-01-18T00:00:00ZOptically triggered global shutter image sensor using single-photon avalanche diodes
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.0017
<p>A novel optically triggered global shutter image sensor using single photon avalanche diodes (SPAD) is proposed. An optical signal with a switching frequency of 100 MHz illuminates SPADs and acts as both a shutter and reset signal source by means of free space optics. Each image sensor pixel contains a front side illuminated SPAD, while a pinned photodiode is used to collect the scene's light from the chip back side to increase the pixel fill factor. The pixel is designed and post layout simulated in 90 nm complementary metal oxide semiconductor technology. Moreover, the jitter performance of 76.2 ps (excluding SPAD and light source jitter) is achieved. The image sensor pixel pitch is 90 µm with 2.27 mW power consumption per pixel with a fill factor of above 90%. The image sensor pixel can take 64 different frames at the rate of 50 Mfps and store until the global readout phase.</p>2018-05-01T00:00:00ZMixed-signal demodulator for IEEE 802.15.6 IR-UWB WBAN energy detection-based receiver
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0350
<p>A mixed-signal baseband demodulator for IEEE 802.15.6 impulse-radio ultra-wideband (IR-UWB) wireless body area network (WBAN) energy detection-based receiver is presented. It considers M-ary pulse position modulation (PPM) signalling format conforming to the IEEE 802.15.6 WBAN standard. The demodulator utilises ‘integrate-and-digitise’ approach employing simple mixed-signal circuits. The design is implemented in 0.18 μm CMOS technology operating at 1.8 V supply. The demodulator consists of a mixed-signal windowed integrator, a single-ended successive approximation register analogue-to-digital converter followed by a digital back-end. Further, its performance evaluation is carried out for 2-ary and 16-ary PPM signalling in different WBAN channels.</p>2018-04-09T00:00:00ZManchester-encoded data transmission circuit integrated by metal–oxide TFTs suitable for 13.56 MHz radio-frequency identification tag application
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0499
<p>This study proposes a Manchester-encoded data transmission circuit suitable for 13.56 MHz radio-frequency identification (ID) tags integrated by indium–zinc–oxide thin-film transistors (TFTs). All the modules in the circuit are only constructed by two types of logic units: NOT gate and NOR gate. The 16 bit ID data are stored in the read-only-memory circuits realised by a fixed TFTs array. The 16 bit ID data are encoded by Manchester module as the output of the Manchester-encoded data transmission circuit with a bit rate of 103 kbps. The chip area is 6.5 mm<sup>2</sup> with the total number of gates as 76 and the sum of the transistors as 300. Moreover, the power consumption is 3.8 mW at VDD = 5 V.</p>2018-04-13T00:00:00ZLow-power sample and hold circuits using current conveyor analogue switches
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0411
<p>This study presents low-power sample and hold (S/H) circuits using second-generation current conveyor (CCII). Unlike previous S/H circuits, switch of the proposed S/H circuits can be obtained using CCII which works as current conveyor analogue switch (CCAS). The state of CCAS is controlled by sampling pulse that can be applied via its bias current source. The proposed S/H circuits offer low-power consumption, high-speed and absent from non-overlapping clock signal requirements. Three configurations of S/H circuit are proposed, namely single-ended S/H, differential S/H and serial-to-parallel S/H circuits. The proposed S/H circuits have been simulated using 0.18 µm complementary metal oxide semiconductor (CMOS) process from Taiwan semiconductor manufacturing company (TSMC). The simulation results are used to confirm the workability of the proposed structures.</p>2018-01-30T00:00:00ZLow-power low data rate FM-UWB receiver front end
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0507
<p>This study introduces a frequency modulated ultra-wideband (FM-UWB) receiver optimised for low power and fast start-up. The receiver consists of a front end amplifier converting a frequency modulated signal to an amplitude modulated signal which is applied to an envelope detector. The receiver front end is for 500 MHz channels centred at 3450 and 3950 MHz. The amplifier uses passive gain and four cascaded gain stages to achieve high radio-frequency gain without the need for super-regeneration. By simplifying the architecture this way, the front end has a 5 μs wake-up time to enable efficient duty-cycling. The measured front end receives a signal at −68 dBm while consuming 600 μW of power (excluding a test buffer) from a 1 V supply. Fabrication was done using the IBM 130-nm CMOS technology on a 1 mm × 1 mm loose die.</p>2018-01-11T00:00:00ZLinearisation technique for low-voltage tuneable Nauta's transconductor in Gm−C filter design
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0177
<p>A low-distortion, low-voltage transconductor based on Nauta's inverter-type transconductor is proposed. The transconductor's core MOSFETs are pushed into a strong inversion region under a low-voltage supply utilizing a level shifter consisting of a linear resistor and a MOSFET current source. The transconductor's linearization relies on summing a decreasing <i>G<sub>m</sub> </i> characteristic with an increasing counterpart to obtain an overall flat <i>G<sub>m</sub> </i> characteristic. The non-ideal decreasing <i>G<sub>m</sub> </i> is exploited from a non-linear behaviour of the triode–MOS current source that restricts a |<i>V</i> <sub>GS</sub>| increment of the core strongly-inverted MOSFET quartet while its increasing-<i>G<sub>m</sub> </i> counterpart found in another weakly-inverted auxiliary MOSFET quartet. The MOSFET current source plays significant role in the linearization process where it has to be in a triode mode of either a strong, weak or moderate inversion region. Simulation results are provided to verify the feasibility of the proposed transconductor with a 5th-order Chebyshev lowpass filter in a 0.18 µm CMOS process. The filter operates under a 0.5 V supply (the ratio <i>V</i> <sub>DD</sub>/<i>V</i> <sub>TH</sub> = 1.19) with a continuous bandwidth tuning from 500 kHz to 2.8 MHz. The proposed filter with a nominal 1.4 MHz bandwidth and a 430 mW power consumption renders the two-tone SFDR of 64.9 dB.</p>2018-01-11T00:00:00ZInternal write-back and read-before-write schemes to eliminate the disturbance to the half-selected cells in SRAMs
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0227
<p>In static random access memory (SRAM), some cells are not selected for writing, but due to the distribution of the word line signals in the SRAM array, their word line signal is activated. Therefore, they may be mistakenly written. Such cells are called half-selected cells. This study presents two schemes, one for single-ended and the other for differential sensing SRAMs, to eliminate the half-selection disturbance. In the first proposed scheme, the content of the desired row of the SRAM array is read before the write operation and is written back on the corresponding write bitlines. This operation results in eliminating the possibility for noise to be written onto the half-selected cells. In the second scheme, a simple read operation is performed before the write operation. The authors applied their half-selection resilient schemes to 8 and 6 T SRAMs. Simulation results show that in the presence of radioactive particles, by applying their write-back scheme to 8 T SRAM and their read-before-write scheme to the conventional 6 T SRAM, the failure rate is reduced from an average of 56 and 20%, respectively, to 0. The proposed schemes do not degrade write-ability of the SRAM cells, and are bit-addressable. Moreover, their proposed schemes consume smaller amounts of power compared with their rivals.</p>2018-02-05T00:00:00ZIntegrated routing scheme and inverter switch to develop a mobile controlled energy saving system
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.0086
<p>The solutions of inverter switch and routing scheme are integrated to develop a mobile controlled energy saving system (MCESS). For the transient response problem of an n-channel metal-oxide-semiconductor field-effect transistor acting as an invert switch, and a routing scheme is solved for developing the MCESS. It can be claimed that all the mentioned previously schemes are very challenge for addressing the problems in the design of an analogue processing circuit and the implementation of Android applications (or Apps). The developed MCESS is experimentally verified automatically switch for adjusting the energy output appropriately. A control system with a solution of MCESS can replace the traditional sustainable energy systems, and obtain much longer lifetime and a steady state of the storage equipment. Furthermore, the proposed MCESS integrates Apps developed on a smart device using the Android platform with different wireless protocols, such as WiFi, Bluetooth for controlling the system with contactless. Moreover, there much experience in the development of MCESS is provided audiences with useful materials, for example a routing solution that employs wireless local area network with the WiFi protocol is implemented to transmit packets of the regulator circuit and the instant feedback display.</p>2018-04-25T00:00:00ZImproved convergent distributed arithmetic based low complexity pipelined least-mean-square filter
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.0041
<p>This study presents an improved convergent distributed arithmetic (DA)-based low complexity pipelined least-mean-square filter. The concept is based on a convex combination of two adaptive filters (ADFs) where the convergence performance of the combined filter is adjusted by the step-sizes of ADFs. The proposed technique replaced two ADF units by a single unit of the DA-based ADF. Further reduction in hardware complexity is achieved by sharing the filter partial products. Moreover, a bit-level coefficient update unit is employed to minimise its hardware complexity. In addition, a novel low-cost strategy is presented to improve the convergence performance of the proposed filter by comparing the time-window corresponding to the maximum correlation of delayed error signals <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mi>e</mml:mi> <mml:mo>(</mml:mo> <mml:mi>n</mml:mi> <mml:mo>−</mml:mo> <mml:mi>m</mml:mi> <mml:mo>)</mml:mo> </mml:math> </script> with a pre-defined window with <i>n</i> being time instant and <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mi>m</mml:mi> <mml:mo>∈</mml:mo> <mml:mo>[</mml:mo> <mml:mn>1</mml:mn> <mml:mo>,</mml:mo> <mml:mn>2</mml:mn> <mml:mo>]</mml:mo> </mml:math> </script>. Compared with the best existing scheme, the proposed design offers 46.42% fewer adders, 36.69% fewer registers and 18.75% fewer multiplexers for a 64th-order filter. Application specific integrated circuit synthesis results show that the proposed design occupies 37.10% less chip-area and consumes 24.79% less power. In addition, the proposed design provides 20.35% less area-delay-product and 4.76% less energy-per-sample for 64th order with the fourth-order base unit over the best existing scheme.</p>2018-04-20T00:00:00ZIdentification of DC–DC buck converter dynamics using relay feedback method with experimental validation
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0542
<p>Accurate dynamics of power converters are necessary to achieve good control performance. In this study, the dynamical model of the DC–DC buck converter is identified by the relay feedback method. The relay is connected in the closed loop to produce a limit cycle output. The important information of the oscillatory output is used for the identification. The relay is approximated using dual-input describing function (DIDF) in the mathematical modelling. DIDF can handle symmetric and asymmetric limit cycle outputs. The converter is modelled as a second-order plus dead-time system. Using the gain and phase angle criteria, analytical expressions are derived to estimate the dynamics. The converter dynamics obtained from the proposed method are compared with that estimated using the state-space averaging method. The model is also identified from the real-time experiment. To check the efficacy of the identified model, a model validation test is performed.</p>2018-04-13T00:00:00ZHigh-speed analogue sampled-data signal processing for real-time fault location in electrical power networks
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0212
<p>The emulation of low-loss or lossless one-dimensional (1D) or 2D transmission mediums using analogue sampled-data signal processing is presented. Based on discrete-time wave propagation simulation, transmission lines are emulated with many elementary identical delay elements, implemented by simple equivalent switched-capacitor (SC) circuits. The accuracy and limitations of this discrete time model are studied in the frame of power network fault location using electromagnetic time-reversal principle. The sensitivities to non-ideal effects usually plaguing analogue CMOS SC circuits, such as amplifier finite open-loop gain, offset, and parasitic charge injection due to clock feedthrough, are evaluated in the same context. It is shown that the SC line emulation is well suited to the presented fault location technique and considerably reduces the fault location time (by a factor up to 100) in comparison to standard digital solutions, allowing fault location resolutions of typically 1% within a few hundred milliseconds. These expectations are confirmed by measurements realised on the presented line model integrated-circuit, implemented in an AMS 0.35 μm CMOS process. The speed improvement obtained through the presented method is essential, potentially allowing real-time fault management in power grids.</p>2018-03-09T00:00:00ZHigh-order realisation of MOSFET-only band-pass filters for RF applications
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0442
<p>The authors present two new metal oxide semiconductor field effect transistor (MOSFET)-only second-order voltage and transadmittance-mode band-pass filters (BPFs) employing only five transistors without using any passive elements such as a resistor, a capacitor, and an inductor. As a result, both proposed circuits possess low-power consumption and occupy small chip area. The first proposed filter enjoys low output impedance and offset cancellation for voltage-mode operation while the second proposed filter has low supply voltage. The centre frequency of both proposed filters can be electronically tuned by varying biasing voltage. To demonstrate the performance of the proposed filters, effects of output transconductance of transistors have been investigated and equations of input referred noise have been obtained. Furthermore, fourth-order voltage and transadmittance-mode BPF which is derived the first proposed filter is presented and its simulation results are given. All proposed filters are laid-out in the Cadence environment using Taiwan semiconductor manufacturing company (TSMC) 0.18 µm complementary metal oxide semiconductor (CMOS) technology parameters. The required chip area of the fourth-order voltage and transadmittance-mode band-pass filter is 1100 μm<sup>2</sup> and the power consumption is about 436 µW.</p>2018-02-05T00:00:00ZHardware implementation and VLSI design of spectrum sensor for next-generation LTE-A cognitive-radio wireless network
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0292
<p>This paper presents reconfigurable and hardware-efficient VLSI architecture of time domain cyclostationary-feature detector (TCD) for spectrum sensing in the cognitive-radio wireless network. It incorporates new architecture for autocorrelator that supports the entire range of subcarriers used by orthogonal frequency division multiplexing signals compliant to 4G LTE-Advanced wireless network. A novel scheme of overflow/underflow protection is proposed for the coordinate rotation digital computer engine of TCD. Additionally, hardware-efficient techniques have been introduced for the multiply-&-accumulate and accumulator architectures of suggested TCD design. Real-world signals are captured using universal software radio peripheral devices and are fed to its FPGA prototype. An application specific integrated circuit synthesis and post-layout simulation of the proposed detector have been performed using 65 nm-CMOS technology and it occupies 0.32 mm<sup>2</sup> of core area and consumes total power of 18.5 mW at 100 MHz clock frequency. In comparison with the state-of-the-art works, the proposed detector requires 34 and 93% lesser hardware resource and memory, respectively</p>2018-02-20T00:00:00ZGeneral modular adder designs for residue number system applications
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0470
<p>Modular adders are very crucial components in the performance of residue number system-based applications. Most of the work published so far has been restricted to modulo <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mo>(</mml:mo> <mml:msup> <mml:mn>2</mml:mn> <mml:mi>n</mml:mi> </mml:msup> <mml:mo>±</mml:mo> <mml:mn>1</mml:mn> <mml:mo>)</mml:mo> </mml:math> </script> adders or modulo-specific adders. Less work has been dedicated to modulo-generic adders. This work presents new designs for modulo <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mo>(</mml:mo> <mml:msup> <mml:mn>2</mml:mn> <mml:mi>n</mml:mi> </mml:msup> <mml:mo>±</mml:mo> <mml:mi>K</mml:mi> <mml:mo>)</mml:mo> </mml:math> </script> adders, where <i>K</i> is any integer in the range of <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mn>3</mml:mn> <mml:mo>≤</mml:mo> <mml:mi>K</mml:mi> <mml:mo><</mml:mo> <mml:msup> <mml:mn>2</mml:mn> <mml:mrow> <mml:mi>n</mml:mi> <mml:mo>−</mml:mo> <mml:mn>1</mml:mn> </mml:mrow> </mml:msup> </mml:math> </script>. The proposed structure merges two binary adder structures and maximises sharing of components, wherever possible. This merger permits shorter cell-interconnections, which results in space wastage reduction. Additionally, tristate-based multiplexers (MUXs) are used in lieu of the more demanding gate-based MUXs. As examined over a very practical range of <i>n</i>, <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mn>7</mml:mn> <mml:mo>≤</mml:mo> <mml:mi>n</mml:mi> <mml:mo>≤</mml:mo> <mml:mn>15</mml:mn> </mml:math> </script>, and based on a 65 nm VLSI realisation, the circuit layouts of the proposed adders outperform considerably the most recent and competitive functionally identical published works. On average, the proposed designs have shown reductions in area, time, power, and energy of 23.7, 13.8, 22.9, and 33.6%, respectively.</p>2018-01-31T00:00:00ZGate diffusion input based 4-bit Vedic multiplier design
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0454
<p>A multiplier is one of the key hardware blocks in most of the processors. Multiplication is a lengthy, time-consuming task. Vedic multiplication in field programmable gate array implementation has been proven effective in reducing the number of steps and circuit delay. Conventionally at the circuit level, complementary metal oxide semiconductor (CMOS) logic is used to design a multiplier. In CMOS circuits, the area is always an issue. Gate diffusion input (GDI)-based logic has been explored in the literature to reduce the number of transistors for various logic functions. Thus, Vedic mathematics, on the one hand, simplifies the multiplication process and reduces the delay; while on the other hand, GDI technique helps in minimising the transistor count (TC) and reduction in power. Therefore, this study puts forth a GDI logic-based 4-bit Vedic multiplier. To study the effectiveness of the GDI logic, the transient response of a 2-bit Vedic multiplier using CMOS and GDI is compared. For the 4-bit Vedic multiplier, two design approaches are taken into consideration. The performance of these circuits is analysed in terms of average power dissipation, delay, and TC. The effect of supply voltage scaling is also studied. The circuit simulations are carried out at 130 nm for bulk metal oxide semiconductor field effect transistor predictive technology model-based device parameters.</p>2018-04-12T00:00:00ZFault-tolerant design and analysis of QCA-based circuits
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0505
<p>Emerging nanoscale computing structure quantum-dot cellular automata (QCA) is evolving as a possible replacement for complementary metal–oxide–semiconductor technology in near future. Being a new technology, it is prone to various types of fabrication-related faults and process variations. So, QCA-based circuits are prone to errors, and therefore pose significant reliability-related issues. Hence, there is an emerging need to design fault-tolerant QCA-based circuits to mitigate the reliability issues. This study first presents QCA-based new designs of 2-input Exclusive-OR gate and 1 bit full adder using conventional design approach without redundant QCA cells. Then, the fault tolerance has been implemented in these designs by introducing redundant QCA cells. The proposed circuits exhibit significant improvements in fault-tolerant capability against cell omission, misalignment, displacement, and extra cell deposition defects. The proposed fault-tolerant designs have been compared with existing designs in terms of generalised design metrics of QCA circuits. Energy dissipation results have been computed for the proposed fault-tolerant circuits using accurate QCAPro power estimator tool. Influence of temperature variations on the polarisation of the proposed fault-tolerant circuits has also been investigated. The functionality of the proposed circuits has been verified with QCADesigner version 2.0.3 tool.</p>2018-03-13T00:00:00ZElastic buffer evaluation for link pipelining under process variation
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0394
<p>Network-on-chip (NoC) adopted for many-core intercommunications may face long link delay and power consumption limitations. A proven solution is to segment long links with storage elements or repeaters. Besides, a new design paradigm called elastic has been considered in the literature, which seems suitable for NoC designs. In this study, the authors explore the benefit of various elastic-buffer (EB) structures to be used for link pipelining. They study elastic handshaking protocols and explore various elastic buffer designed to be used in NoC era. They propose to use synchronous elastic flow (SELF) handshaking protocol for link pipelining. Results show elastic buffer structure based on SELF-handshaking protocol, which can run at least with 21% higher frequency, has 25% less delay and consumes 8% less power compared with other proposed designs. They have explored the process variation issues with various scenarios on seven different structures. They have improved the SELF-elastic buffer, which is more resilient against process variation, proposing two new structures. The new proposed structures exhibit about 5% better performance and 13% less power delay product variation in average.</p>2018-03-12T00:00:00ZEfficient digit-serial modular multiplication algorithm on Field Programmable Gate Array CLA Carry-Lookahead Adder
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0300
<p>For cryptographic applications, such as DSA, RSA and ECC systems, the crypto-processors are required to perform modular multiplication (MM) on large integers over Galois field. A new digit-serial MM method is presented by using a variable size lookup table. The proposed modular multiplier can be designed for any digit-size <i>d</i> and modulus <i>M</i> which only requires simple operations such as addition and shifting. Based on theoretical analysis, the efficient digit-serial MM architecture requires the latency of <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mi>O</mml:mi> <mml:mo>(</mml:mo> <mml:mo>⌈</mml:mo> <mml:mi>n</mml:mi> <mml:mrow> <mml:mo>/</mml:mo> </mml:mrow> <mml:mi>d</mml:mi> <mml:mo>⌉</mml:mo> <mml:mo>+</mml:mo> <mml:mi>d</mml:mi> <mml:mo>+</mml:mo> <mml:mn>2</mml:mn> <mml:mo>)</mml:mo> </mml:math> </script> clock cycles. As a result, the developed architecture can achieve less area–delay product on hardware when compared with previous designs.</p>2018-03-28T00:00:00ZEfficient design of coplanar ripple carry adder in QCA
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.0020
<p>An optimal quantum-dot cellular automata (QCA) design for full adder (FA) based on an optimal three-input exclusive-OR (XOR) gate is presented. This XOR structure utilises a new configuration of cells unlike traditional gate-level approaches. The coplanar QCA FA spans over <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mn>0.03</mml:mn> <mml:mspace></mml:mspace> <mml:mrow> <mml:mi>μ</mml:mi> </mml:mrow> <mml:msup> <mml:mrow> <mml:mi>m</mml:mi> </mml:mrow> <mml:mn>2</mml:mn> </mml:msup> </mml:math> </script> and delays of 0.5 clock cycles with 40 cells. It achieves total energy dissipation as low as 0.144 eV at 1.5<script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:msub> <mml:mi>E</mml:mi> <mml:mi>k</mml:mi> </mml:msub> </mml:math> </script> energy level. The utility of proposed gate is leveraged to design a ripple-carry adder (RCA) as a specific application. For performance evaluation, the authors use traditional cost metrics and QCA-specific cost function. Results show that proposed <i>n</i>-bit RCA outperforms most of the best state-of-the-art designs known in the literature. For example, cell count (area consumption) of 4, 8, and 16 bit adders is 62% (70%), 66% (84%), and 70% (86%) less than the best coplanar RCA design results. In addition, by taking the new cost metrics into account, it is found that proposed adder performs fairly well as compared to the previous adders too. These designs are realised and simulated using QCADesigner.</p>2018-03-05T00:00:00ZEffect of doping on the performance of multiple quantum well infrared photodetector
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0011
<p>This study theoretically analyses the performance of multiple quantum well infrared photodetector mainly with the variation of active layer doping. However, the effect of temperature and applied bias has also been studied. Results show that the effect of doping on the responsivity is significant whereas on the dark current is less significant. Effect of temperature on the dark current is more significant compared with that of doping concentration. Moreover, concerning the detectivity of the device, choice of doping plays a significant role on the detector.</p>2018-02-21T00:00:00ZDownscaling AsTeGeSiN threshold switching devices for high-density 3D memories
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0459
<p>In high-density three-dimensional (3D) memory technology, a stacking method is used to create memory devices and access devices at the intersections of bit lines and word lines. For this application, access devices should have a high on/off ratio, high current density for writing cycles, and high endurance. Consequently, an arsenic–tellurium–germanium–silicon nitride compound (AsTeGeSiN) threshold switching device with a high current density of 10<sup>4</sup> A/cm<sup>2</sup> above the threshold voltage (<i>V</i> <sub>th</sub>) is reported as a good candidate for use in access devices. In addition, scaling down of access devices as well as memory devices is essential for high-density 3D memories. However, in AsTeGeSiN threshold switching devices, fast degradation by pulse cycling in smaller devices is observed. To find the main cause of fast degradation by pulse cycling in smaller devices, the low-frequency noise properties are examined. The rapid increase in the trap density (<i>N</i> <sub>T</sub>) in small devices is the main cause of fast degradation by pulse cycling in AsTeGeSiN devices. On the basis of this evaluation, the author examines the effect of annealing temperature and annealing time on the pulse endurance in smaller devices. Using an annealing temperature of ∼600°C improves the cycling endurance of smaller devices.</p>2018-03-09T00:00:00ZDigital LDO modelling techniques for performance estimation at early design stage
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0429
<p>This work studies the transient responses and steady-state ripples of digital low dropout (LDO) voltage regulators. Simulation models as well as closed-form expressions are provided for estimating the LDO output settling behaviour after load current or reference voltage changes. Estimation equations for the magnitude and frequency of LDO output steady-state ripples are also presented. The accuracy of the developed models is verified by comparing estimation data with results obtained from circuit simulations. The use of the developed estimation equations in design space exploration is also demonstrated.</p>2018-03-09T00:00:00ZDevelopment of integrated microsystem for hydrogen gas detection
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0243
<p>A low-power microelectromechanical system-based metal–oxide gas sensor along with integrated signal conditioning unit is presented in this study to detect and quantify the variation of H<sub>2</sub> gas concentrations. The interface circuit controls the sensor operating temperature, measures the H<sub>2</sub> gas concentration, contributes a user-friendly interface and can be used with any suitable sensor network. A PIC16F877A microcontroller has been used for this purpose. The temperature of the sensors was stabilised by controlling the actuating voltage of the microheater. Temperatures of the microheater depend on the output voltage of the digital-to-analogue converter (DAC) and were measured by sampling the heater resistance through the use of a voltage divider and analogue-to-digital converters (ADCs). A microcontroller accordingly adjusts the output of DAC's in order to apply the appropriate steering voltage to the heaters. The method employed to measure the concentration of gases is to sample the voltage drop over the resistances of the sensors by ADCs. Alarming system for safety measure was also implemented in this design. The preventive action was taken by introducing an additional feature of wireless communication by sending short message service via global system for mobile modem to the designated emergency number.</p>2018-02-05T00:00:00ZDesign techniques of all-digital arithmetic units for time-mode signal processing
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0327
<p>This study provides a comprehensive treatment of the design techniques of all-digital arithmetic units for time-mode signal processing. The arithmetic units investigated include time polarity detectors, time absolute-value generators, time adders, time baluns, time amplifiers, time quantisers, time registers, and time integrators. The principle, circuit implementation, constraints and limitations of these units are investigated in detail. An emphasis is given to time adders and time integrators. An in-depth study of time adders constructed from switched delay units, dual discharge paths, and unidirectional gated delay lines is provided. It is followed with the presentation of three time registered evolved from these time adders. Three time integrators developed from the preceding time adders and time registers are studied and their characteristics are compared. Finally, the design of a first-order <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mi>Δ</mml:mi> <mml:mi>Σ</mml:mi> </mml:math> </script> time-to-digital converter utilising these arithmetic units is presented.</p>2018-03-26T00:00:00ZDesign of Small Size and High Sensitive Less-Invasive Wireless Blood Pressure Sensor using MEMS Technology
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.0013
2018-05-15T00:00:00ZDesign and analysis of an ultra-thin crystalline silicon heterostructure solar cell featuring SiGe absorber layer
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0132
<p>Here, the authors studied a silicon–germanium (Si<sub>1−<i>x</i> </sub>Ge<i> <sub>x</sub> </i>) absorber layer for the design and simulation of an ultra-thin crystalline silicon solar cell using Silvaco technology computer-aided design. Seeking ways to design and fabricate solar cells using 100 μm thicker silicon substrates is the subject of intense research efforts among the photovoltaic (PV) community. The aim is to further reduce the substrate thickness to 20 μm without compromising the efficiency of the solar cell. A thin layer of SiGe film with the Ge composition of 15% has been introduced in this work that assists in absorbing the longer wavelength of the sunlight spectrum. The effects of the doping concentration and absorber layer thickness on the conversion efficiency have been examined. The simulated results exhibited significant enhancement in the sunlight absorption as compared to the reference structure based on crystalline silicon. The highest efficiency of 16.8% with an overall solar cell thickness of ∼26 μm has been observed. The proposed heterostructure solar cell design will support the industrial development of an efficient, low-cost, shorter energy payback time, and light-weight PV technology for its widespread implementation.</p>2018-01-05T00:00:00ZDesign and analysis of a logic model for ultra-low power near threshold adiabatic computing
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0386
<p>The behaviour of the adiabatic logic in the near threshold regime has been analysed in depth in this study. Near threshold adiabatic logic (NTAL) style can perform efficiently using a single sinusoidal power supply which reduces the clock tree management and enhances the energy saving capability. Power dissipation, voltage swing, effect of load, temperature, frequency etc. of NTAL circuits have been detailed here. Extensive CADENCE simulations have been done in 22 nm technology node to verify the efficacy of the proposed model. A power clock has been generated based on a switched capacitor regulator to drive the complex NTAL circuits. Analytical and simulated data match with high accuracy which validates the proposed adiabatic logic style in the near threshold regime. A significant amount of energy can be saved by the adiabatic logic with or without considering the power dissipation of the clock generator.</p>2018-02-01T00:00:00ZDesign and analysis of CMOS RCG transimpedance amplifier based on elliptic filter approach
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0449
<p>This study presents a new design of compact transimpedance amplifier (TIA) for optical communication applications. By adopting the regulated common gate (RCG) topology, the proposed amplifier is designed and synthesised based on a third-order elliptic filter approach. Implemented in 0.13 μm complementary metal oxide semiconductor technology, the post layout simulation results provide 50 dB Ω of direct current gain, 15 GHz of bandwidth, <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mn>20</mml:mn> <mml:mspace></mml:mspace> <mml:mrow> <mml:mi>pA</mml:mi> </mml:mrow> <mml:mrow> <mml:mo>/</mml:mo> </mml:mrow> <mml:msqrt> <mml:mrow> <mml:mi>Hz</mml:mi> </mml:mrow> </mml:msqrt> </mml:math> </script> as an input referred noise current performance. The proposed RCG TIA occupies a <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mn>19</mml:mn> <mml:mo>×</mml:mo> <mml:mn>36</mml:mn> <mml:mspace></mml:mspace> <mml:mrow> <mml:mi>μ</mml:mi> </mml:mrow> <mml:msup> <mml:mrow> <mml:mi>m</mml:mi> </mml:mrow> <mml:mn>2</mml:mn> </mml:msup> </mml:math> </script> while consuming 5.34 mW under 1.2 V supply voltage, only.</p>2018-02-15T00:00:00ZDesign Procedure for Multifinger MOSFET Two-stage OTA with Shallow Trench Isolation Effect
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0419
2018-03-19T00:00:00ZDC Modeling of SOI Four-Gate Transistor (G4FET) for Implementation in Circuit Simulator Using Multivariate Regression Polynomial
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.0059
2018-04-27T00:00:00ZCompact thermal noise model for enhancement mode N-polar GaN MOS-HEMT including 2DEG density solution with two sub-bands
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0226
<p>A 135 nm gate length-based low noise enhancement mode N-polar double deck T-shaped gate Gallium Nitride (GaN) Metal Oxide Semiconductor (MOS)-high electron mobility transistor with double insulating layer of high-<i>k</i> dielectrics ZrO<sub>2</sub>/HfO<sub>2</sub> is proposed. The device exhibits maximum transconductance of 0.55 S/mm, maximum drain current density of 1.4 A/mm and minimum noise figure (NF<sub>min</sub>) of 0.72 dB at 20 GHz. A compact model for Two Dimensional Electron Gas (2DEG) density is developed by explicit solution of surface potential and Fermi level by considering first two sub-bands of triangular quantum well without using any numerical methods. Based on the surface potential drain current, intrinsic charge, gate capacitance, small signal and thermal noise models are developed. To validate the proposed numerical model, the results are calibrated with TCAD device simulation results and available experimental data from literatures.</p>2018-03-14T00:00:00ZCalibration method to reduce the error in logarithmic conversion with its circuit implementation
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0315
<p>Here, based on Mitchell's logarithmic conversion, the authors propose a fast calibration method using a fixed binary code with case judgement, which suppresses the conversion error. The authors developed a highly paralleled circuit serving the proposed calibration method. Differential cascade voltage switch logic (DCVSL) is used to work in both high-speed logic and adiabatic logic and trade-off between power dissipation and operation speed. In addition, a low-cost adiabatic clock generator without any passive component is presented to support a four-phase sine clock for the adiabatic logic operation. An 8-bit logarithmic converter is designed in TSMC 180 nm CMOS. Post-simulation results show that the proposed calibration can reduce the conversion error to 1.55% based on Mitchell's algorithm, the power dissipation varies between 1.12 and 3.709 mW, and the delay is 1.82 ns under operational DCVLS.</p>2018-01-05T00:00:00ZCMOS-based high-order LP and BP filters using biquad functions
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0493
<p>This study proposes the complementary metal–oxide–semiconductor (CMOS)-based current-mode high-order active low-pass (LP) and band-pass (BP) filters using biquad functions. The passive RLC Chebyshev ladder filters were used as the prototype, and the mesh- and nodal-analysis methods to derive the biquad functions. The CMOS-based transistor-level biquad circuits were subsequently realised from the biquad functions. The high-order active LP and BP ladder filters were then synthesised from an amalgamation of the biquad circuits. Simulations were carried out to verify the performance and functionality of the LP and BP ladder filters. The results revealed that the proposed ladder filters were operable in the high-frequency range and electronically tunable, given a low-voltage supply of 1 V for the entire circuit. The proposed filters could also achieve the LP frequency response of 300 kHz–30 MHz and BP centre frequency of 200 kHz−20 MHz by means of the bias current (<i>I</i> <sub>B</sub>) manipulation from 1 to 100 µA. Moreover, the multi-tone simulations were undertaken to assess the filtering performance of the proposed filters and the results are agreeable with the design specifications.</p>2018-01-12T00:00:00ZCMOS MO-CFDITA Based Fully Electronically Controlled Square/Triangular Wave Generator with Adjustable Duty Cycle
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0553
2018-04-18T00:00:00ZBroadband reconfigurable matching network using a non-uniform transmission line
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0512
<p>In this study, the authors propose the use of distributed elements interconnected with switches to construct a reconfigurable matching network (RMN). Several RMNs are constructed using tunable lumped elements. However, this technique increases the system complexity because of the use of digital-to-analogue converters and synthesis algorithms. In this study, the proposed RMN employs a non-uniform transmission line with adjustable characteristic impedances, which are controlled by opening or closing the switches. While previous studies on non-uniform transmission lines have aimed to investigate the fixed configurations, this topology is designed to be an RMN that satisfies the design challenges. The maximum dimension is 0.2 times the guided wavelength of the low operational frequency, and five switches are used; however, the matchable impedances cover an extensive range of the Smith chart, and the RMN successfully tunes inherently unmatched antennas to operate at a target frequency band that depicts a fractional bandwidth of 60%. Additionally, the evaluated results depict that the fabricated RMN illustrates low insertion loss and high transducer gain and that it achieves both antenna-mismatch compensation and antenna-bandwidth extension.</p>2018-03-05T00:00:00ZBit-parallel systolic multiplier over GF(2m) for irreducible trinomials with ASIC and FPGA implementations
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0426
<p>Cryptography in digital world must offer integrity and confidentiality using cryptographic algorithms which mainly involve multiplication operation in finite fields. Various algorithms and architectures are proposed in the literature to obtain efficient finite field multiplications in both hardware and software. Here, a modified interleaved multiplication algorithm with reduced computational complexity is proposed based on a novel pre-computation (PC) technique to perform multiplication over <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mrow> <mml:mi>GF</mml:mi> </mml:mrow> <mml:mo>(</mml:mo> <mml:msup> <mml:mn>2</mml:mn> <mml:mi>m</mml:mi> </mml:msup> <mml:mo>)</mml:mo> </mml:math> </script> for trinomials. Consequently, an <i>m</i>-bit systolic multiplier for trinomials (SMT) is designed by employing the proposed algorithm. Hardware and delay complexity analysis is performed and comparison of the proposed SMT structure with similar multipliers available in the literature is presented. The SMT structure achieves ∼28 and 17% improvement in hardware and area-delay product, respectively, for <i>m</i> = 233 when compared with the best multiplier available in the literature. The functionality of the proposed SMT structure is also verified by implementing on field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) technologies. It can be observed from FPGA and ASIC implementation results that the proposed SMT structure shows improvement in area, power consumption, area-delay, and power-delay products when compared with similar multipliers available in the literature.</p>2018-01-05T00:00:00ZAnalytical modelling of work-function modulated delta-doped TFET to improve analogue performance
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0135
<p>In this study, an analytical model for linearly modulated work-function-based delta-doped single-gate tunnel field-effect transistor (TFET) has been developed to improve the analogue performance. The impact of delta-doped layer and linearly modulated metal gate on different analogue parameters has been investigated extensively. The insertion of heavily doped delta layer in the source region improves ON current and current switching ratio performance significantly as compared to conventional TFET. Similarly, the presence of spatially work-function modulated metal gate reduces subthreshold swing and improves <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:msub> <mml:mi>I</mml:mi> <mml:mrow> <mml:mn>60</mml:mn> </mml:mrow> </mml:msub> </mml:math> </script> performance. The distance of the delta layer from the source–channel interface is optimised to 3 nm to maximise efficiency. The proposed model exhibits much improved analogue performance as compared to conventional TFET and delta-doped TFET. Thus, the model can be viewed as one of the potential replacements for metal–oxide–semiconductor field-effect transistors in ultra-low-power applications. However, the precision of present model is corroborated by using the two-dimensional TCAD Sentaurus simulator.</p>2018-01-29T00:00:00ZAnalytical Modelling and Performance Analysis of Gate Engineered Tri-gate SON MOSFET
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0473
2018-03-07T00:00:00ZAn 114 Hz–12 MHz digitally controlled low-pass filter for biomedical and wireless applications
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0410
<p>This study presents a wide tunable Gm-C low-pass filter for biomedical and wireless applications. The proposed filter was designed using the standard 90 nm complementary metal–oxide–semiconductor technology operating with a balanced supply voltage of 1.2 V. Modified linearisation techniques are used to improve the linearity of the digital programmable operational transconductance amplifiers (DPOTAs) which are used in the filter design. The proposed filter consists of three parallel fourth-order Butterworth sections. Each section is designed and optimised to target a specific band of frequencies. The operation of selecting between the different sections is free of any physical switches. Turning off the unwanted sections is utilised by setting the control bits of the corresponding DPOTAs to zeros. The performance of the proposed filter and DPOTAs is validated through simulation results. The third-order harmonic distortion of the DPOTA remains below −60 dB up to 0.5 V differential input voltage. The simulation results show that the digitally tunable cutoff frequency of the proposed low-pass filter is widely varied in the range of 114 Hz–12 MHz. The proposed filter achieves IIP3 of 28 dBm.</p>2018-03-07T00:00:00ZA Two Stage Current-reused Variable-Gain Low-Noise Amplifier for X-band Receivers in 65nm CMOS Technology
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0538
2018-03-12T00:00:00ZA Placement and Routing Method for Analog Layout Generation Using Modified Cuckoo Optimization Algorithm
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0111
2018-01-31T00:00:00ZA Novel Spintronic Memristor Synapse and Its RWC Learning Algorithm
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0427
2018-01-05T00:00:00Z16-bit 1-MS/s SAR ADC with foreground digital-domain calibration
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0412
<p>This study presents a low-power 16-bit 1-MS/s successive approximation register analogue-to-digital converter (SAR ADC) for medical instrument applications. A foreground digital-domain calibration method simultaneously correcting mismatch errors in capacitive digital-to-analogue converter (CDAC) and ‘segment error’ of split-CDAC array is proposed. The split-CDAC architecture combines a <i>V</i> <sub>cm</sub>-free technique in a floating CDAC scheme. The <i>V</i> <sub>cm</sub>-free technique avoids a power hungry <i>V</i> <sub>cm</sub> generator, and the floating CDAC scheme allows the conversion of a high-voltage input signal with low supply voltage and without a significant attenuation of the input signal. Moreover, a modified direct-switching SAR logic is adopted to improve the conversion speed. The prototype was fabricated in a 0.18 µm 1P6M Complementary Metal Oxide Semiconductor (CMOS) technology, and achieves 86.16 dB signal-to-noise and distortion ratio and an Figure of Merit (FOM) of 0.41 pJ/conversion-step.</p>2018-02-16T00:00:00Z1.2 V, 12.5 MHz fourth-order low-pass filter with 83 dB stopband attenuation using low output impedance source follower in 45 nm CMOS
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0424
<p>A source follower with improved output resistance is proposed. This improvement is achieved using shunt–shunt feedback with the help of a voltage combiner in the feedback loop which helps not only enhancing the gain but achieving reduced distortion due to improved isolation. A high-performance Sallen–Key biquad is implemented using this improved source follower and two capacitors which offer 29.3 MHz of bandwidth and almost 50 dB of stopband attenuation with the power of 2.3 mW. A fourth-order Chebyshev low-pass filter prototype is designed with a cascade of two such biquads in 45 nm complementary metal–oxide–semiconductor (CMOS). A cut-off frequency of 12.4 MHz is obtained with a stopband rejection of more than 83 dB. The power dissipation of the filter is 5.1 mW, at 1.2 V supply, and achieves an in-band third-order intercept point of +26.8 dBm. The in-band input-referred noise is <script type="math/mml"> <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mn>3.4</mml:mn> <mml:mo>(</mml:mo> <mml:mrow> <mml:mi>uV</mml:mi> </mml:mrow> <mml:mrow> <mml:mo>/</mml:mo> </mml:mrow> <mml:msqrt> <mml:mrow> <mml:mi>Hz</mml:mi> </mml:mrow> </mml:msqrt> <mml:mo>)</mml:mo> </mml:math> </script>, resulting in a dynamic range of 78.1 dB.</p>2018-01-29T00:00:00Zpth-order inverse of the Volterra series for multiple-input multiple-output non-linear dynamic systems
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0447
<p>A method to determine the <i>p</i>th-order inverse of the Volterra series of multiple-input multiple-output non-linear dynamic systems is presented; it combines time- and frequency-domain techniques to determine the Volterra series of the inverse as a function of the forward system's Volterra series. The method can be used for continuous and discrete time systems. Each operator of non-linear order <b> <i>n</i> </b> of the inverse is a function of the forward system's operators of non-linear order <b> <i>n</i> </b> and lower. It is shown that the <b> <i>p</i> </b>th-order post-inverse is equal to the <i>p</i>th-order preinverse. For the special case that there are no linear cross terms and that the linear memory effects are negligible the kernels of the forward and inverse models are approximately the same. In an example, an approximate inverse model of a model of a concurrent dual band radio frequency amplifier is derived.</p>2018-01-31T00:00:00Z