Technology Computer Aided Design for Si, SiGe and GaAs Integrated Circuits
The first book to deal with a broad spectrum of process and device design, and modelling issues related to semiconductor devices, bridging the gap between device modelling and process design using TCAD. Presents a comprehensive perspective of emerging fields and covers topics ranging from materials to fabrication, devices, modelling and applications. Aimed at research-and-development engineers and scientists involved in microelectronics technology and device design via Technology CAD, and TCAD engineers and developers.
Inspec keywords: gallium arsenide; circuit CAD; network analysis; Ge-Si alloys
Other keywords: semiconductor industry; technology computer aided design; research and development; microelectronic process technology; SiGe; TCAD; device compact model parameter extraction; circuit analysis; integrated circuit; International Technology Roadmap for Semiconductors
Subjects: Computer-aided circuit analysis and design; Electronic engineering computing; Semiconductor integrated circuit design, layout, modelling and testing
- Book DOI: 10.1049/PBCS021E
- Chapter DOI: 10.1049/PBCS021E
- ISBN: 9780863417436
- e-ISBN: 9780863412226
- Page count: 456
- Format: PDF
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Front Matter
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1 Introduction
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In this chapter, technology development, based on projections of new and emerging TCAD tools and methodologies, that offers exciting opportunities in realising new paradigms for the design-manufacturing interface is presented. It is important to have a better interface between process and product designers that will provide both sides with an understanding of how choices affect the overall chip performance, reliability and yield. As this new interface is created and explored, TCAD tools will find a new relevance in the IC design community. This will create new opportunities for innovation for TCAD research. The role of TCAD in compact model development was also presented.
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2 Technology and TCAD tools
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Today much of the development of semiconductor devices and processes is done by TCAD as it offers unique possibilities in visualisation of processing steps, description of the physical changes and understanding of the interrelation of the process variables. Modelling of processes provides a way to interactively explore the fabrication process, studying the effects of process choices, leading to a 'virtual wafer fabrication' (VWF) design environment. TCAD simulation tools provide a controlled and repeatable numerical experiment that can yield information that cannot be measured experimentally. The main aim of a TCAD simulator tool is to match the simulation methodology as close as possible to the fabrication technology and their integration into the actual fabrication. For TCAD tools to be useful in a practical environment, they must be physically accurate, computationally robust and usable by semiconductor process engineers.
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3 Diffusion and oxidation of SiGe/SiGeC films
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In this chapter, a brief discussion on the nature of point defect-mediated diffusion, boron diffusion in silicon and SiGe, and reasons for strain relaxation in SiGe has been made. Because of the relationship between dopant diffusion and point defect diffusion.both the movement of point defects and dopants need to be modelled simultaneously. It has been shown that boron in strained, low Ge-composition SiGe layers diffuses primarily via an interstitial mediated mechanism. Mobile misfit dislocations can act as a strong interstitial sink but immobile dislocations appear to have very little effect on the point defect population. However, experiments should be performed to determine the segregation coefficient across the Si/SiGe interface as a function of germanium and dopant concentration. Further studies should also be taken up to find more closely the relationship between relaxation and interstitial absorption.
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4 Strain-engineered MOSFETs
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In this chapter, the key scaling limits are identified for MOS transistors, and methods for improving device performance are discussed. For improved short channel effects, creation of shallow source/dram extension (SDE) profiles, the use of retrograde and halo well profiles to improve leakage characteristics and the effect of scaling the gate oxide thickness are discussed in detail. Experimental data and simulations are used to show that although conventional scaling of junction depths is still possible, increased resistance for junction depths below 30 nm results in performance degradation. Fundamental trade-offs and scaling trends in engineering these effects are analysed.
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5 SOI MOSFETs
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The use of TCAD to investigate design and applications of devices based on SOI technology has been reviewed. SOI technology allows integration of high performance innovative devices that can push forward the present frontiers of the CMOS downscaling. As one moves from 0.1 μm generation and below, SOI offers a number of advantages in low power, communication circuits and system-on-chip and may ultimately replace bulk CMOS technology. SOI technology improves per formance over bulk CMOS technology by 25-35 per cent, equivalent to two years of bulk CMOS advances and offers the low power advantages. Indeed some perceived SOI disadvantages (self-heating, hot carriers and early breakdown) are no longer such a significant problem for operation at low voltage. The importance of using strained-Si alongside SOI technology to yield significant improvements in mobility has been highlighted.
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6 Heterostructure bipolar transistors
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In this chapter, the design principle of heterostructure devices has been discussed. Critical issues for numerical modelling of heterostructure devices have been discussed. Several examples of simulation of devices employing SiGe HBTs have been considered. Attention has been given to simulation of various advanced technologies leading to high cut-off frequency and/or low transit time. Good agreement between simulation and measurement provides confidence in the use of device simulation for future device development. Transit time analysis of a SiGe HBT using drift-diffusion (DD), hydrodynamic(HD) and full-band Monte Carlo simulations has been discussed in detail. Detail transit time analysis at low temperature for a SiGe HBT has also been performed, which shows its applicability in low-temperature electronics.
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7 SiGe/SiGeC HBT technology
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A retrospective look at the development and production of SiGe HBTs reveals that significant challenges have been overcome to make SiGe now a mature technology. In this chapter, key developments including the SiGe epitaxial growth process, overall integration methods, and elimination of yield-limiting defects to enable production of highly integrated products have been presented. Optimising the interaction of the EPI layer with its surroundings has enabled the achievement of high bipolar device yield. Integration of HP SiGe HBT with CMOS logic and a host of passive devices has created technologies that are well suited for a broad range of HP communication products. Modular integration approaches, such as the base-after-gate approach, has simplified the development of SiGe HBT technologies. It is observed that use of a modular integration approach enables a quick migration to next generation and derivative technologies easily. Enhancements have been achieved primarily in cost reduction, increased integration, and application specific voltage/power requirements. Vertical SiGe HBTs compatible with SOI CMOS have been discussed. The unique feature of collector voltage pinning in thm Si film was discussed in depth, which gives rise to high breakdown voltage, high Early voltage, and low collector capacitance. The SOI device is promising for a better fT-BVceo trade-off than that from conventional collector scaling in bulk devices. The fabricated devices show the anticipated strong dependence of d.c. and RF characteristics on SOI substrate bias. IBM's and IHP's SiGe and SiGeC BiCMOS technologies that have driven the requirements for the most advanced communication applications have been discussed. As a TCAD example, process and device simulation results for a trench isolated double polySiGe HBT using the process simulator ATHENA and device simulator ATLAS towards SiGe/SiGeC technology development have been presented. Use of TCAD tools for the SiGe/SiGeC technology development is expected to offer the process and device designers significant advantages in time-to-market, cost, power and performance prediction.
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8 MOSFET: compact models
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As the mainstream MOS technology is scaled into the deep sub-micron regime, development of a truly physical and predictive compact model for circuit simulation that covers geometry, bias, temperature, d.c.. a.c., RF, and noise characteristics becomes a major challenge. Well-constructed models, however, without accurate model parameters for the used process, may lead to wrong prediction in circuit simulation. Model parameter extraction, in particular from the device characterisation is crucial and remains as an important practical issue that needs serious attention. The surface-potential is based approach is being developed using solutions of several long-standing problems of compact modelling. These include symmetric linearisation method enabling extremely simple yet accurate expressions for the drain current and terminal charges, non-iterative computation of the surface potential and extension of the model formulation beyond the gradual channel approximation. Approaches to MOSFET compact models have been described. A big advantage of a complete surface-potential-based model is that the overall model consistency is auto matically preserved through the surface potential. Therefore, the number of model parameters can be drastically reduced in comparison with conventional models. The modelling of partially-depleted SOI MOSFETs using the third-generation surface-potential-based models has been discussed. An SP-based model has been shown to be an alternative to the more traditional threshold-voltage-based SOI models. Modelling issues for heterostructure MOSFETs are outlined, which need further attention. A subcircuit model for RF CMOS valid under different bias conditions and RF frequency range up to 20 GHz has been described. The usefulness and accu racy of the n-MOSFET model are discussed. A method to extract the important parameters and fine tuning of the parameters from d.c. and RF measurements is also discussed.
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9 HBT: compact models
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The aim of this chapter has been to provide a background for bipolar compact modelling. The main improvements of the VBIC model over the SGP model is the addition of Early voltage effect, quasi-saturation, substrate parasitic, avalanche multiplication, self-heating and modelling of the parasitic pnp transistor. A methodology to extract and optimise d.c. and a.c. parameters for the VBIC model is developed and applied to SiGe HBTs. The model has been verified and optimized using a VBIC pseudo-code and an excellent agreement has been found. A comparison of the VBIC and SGP model clearly illustrates the weakness of the conventional SPICE Gummel-Poon model when applied to advanced SiGe HBTs. The MEXTRAM model includes a direct coupling between current and charge, thus leading to coupled d.c. and a.c. behaviour. This has the advantage of a physical representation of the device, which facilitates accurate scaling. The MEXTRAM and VBIC bipolar transistor models are comparable for low and medium collector current densities and frequencies. Parameter conversion from MEXTRAM to VBIC can easily be done for the depletion capacitances and d.c. parameters related to low and medium current levels. HICUMs major advantages over other bipolar models are its scalability, simple and process-based/related parameter extraction, predictive capability of process and layout variations, and simple numerical formulation. TCAD tool TRADICA has also been discussed. ANFIS automates RF modelling as it is technology independent, neuro-computing based, intelligent and capable of achieving any predetermined accuracy limit required.
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10 Design and simulation of high-speed devices
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The main purpose of this chapter was to discuss the physical models necessary for simulation of advanced heterostructure devices, such as HBLs or HEMLs. Important material parameters of strained-SiGe have been considered. Comprehensive analytical models for material parameter of strained-SiGe films have been presented. The model equations account for valence band discontinuity, heavy doping effects, valence and conduction band effective densities of states and ionised doping concentration. Minority and majority electron and hole mobilities in the whole range from low to very high electric field have also been discussed in detail. The models are based on computed and experimental data available in the literature. SiGe material parameter models developed can be incorporated in commercially available simulators for simulation of SiGe HBLs. New models for physical properties with respect to material composition and strain conditions owing to lattice mismatch have to be developed.
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11 Passive components
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Analog, mixed-signal and RF continue to be a challenge for digital CMOS designers and manufacturers. The performance is ultimately limited by the accuracy of the passive components in the technology. Conflicting scaling methodologies, complex measurement and modelling support requirements, a multiplicity of interacting features and increasingly complex process integration issues are the challenges to overcome to support the next generation of product designs. The ability to accurately construct and model passives with Qs > 15-20 at frequencies > 10 GHz represents a key enabler for new circuits and products.
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Back Matter
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