IEE Proceedings - Vision, Image and Signal Processing

IEE Proceedings - Vision, Image and Signal Processing

Online ISSN 1359-7108
Print ISSN 1350-245X

Published from 1994-2006, IEE Proceedings - Vision, Image and Signal Processing contained significant and original contributions on computer vision, image processing and signal processing.

This journal was previously known as IET Computer Vision 2007-. ISSN 1751-9632. more..

This journal was previously known as IET Image Processing 2007-. ISSN 1751-9659. more..

This journal was previously known as IET Signal Processing 2007-. ISSN 1751-9675. more..

This journal was previously known as IEE Proceedings I (Communications, Speech and Vision) 1989-1993. ISSN 0956-3776. more..

This journal was previously known as IEE Proceedings F (Radar and Signal Processing) 1989-1993. ISSN 0956-375X. more..

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Area efficient FIR filters for high speed FPGA implementation
- Author(s): K.N. Macpherson and R.W. Stewart
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- p. 711 –720 (10)
  A new algorithm that synthesises multiplier blocks with low hardware requirement suitable for implementation as part of full-parallel finite impulse response (FIR) filters is presented. Although the techniques in use are applicable to implementation on application-specific integrated circuit (ASIC) and Structured ASIC technologies, analysis is performed using field programmable gate array (FPGA) hardware. Fully pipelined, full-parallel transposed-form FIR filters with multiplier block were generated using the new and previous algorithms, implemented on an FPGA target and the results compared. Previous research in this field has concentrated on minimising multiplier block adder cost but the results presented here demonstrate that this optimisation goal does not minimise FPGA hardware. Minimising multiplier block logic depth and pipeline registers is shown to have the greatest influence in reducing FPGA area cost. In addition to providing lower area solutions than existing algorithms, comparisons with equivalent filters generated using the distributed arithmetic technique demonstrate further area advantages of the new algorithm.
Framework for FPGA-based discrete biorthogonal wavelet transforms implementation
- Author(s): I.S. Uzun and A. Amira
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- p. 721 –734 (14)
  The discrete wavelet transform has taken its place at the forefront of research for the development of signal and image processing applications. These wavelet-based approaches have outperformed existing strategies in many areas including telecommunication, numerical analysis and, most notably, image/video compression. The authors present an investigation into the design and implementation of 1-D and 2-D discrete biorthogonal wavelet transforms (DBWTs) using a field programmable gate array (FPGA)-based rapid prototyping environment. The proposed architectures for DBWTs are scalable, modular and have less area and time complexity when compared with existing structures. FPGA implementation results based on a Xilinx Virtex-2000E device have shown that the proposed system provides an efficient solution for the processing of DBWTs in real-time.
Effective correlation vector quantisation algorithm and its VLSI architecture
- Author(s): D. Wang ; N. Yu ; Y. Gao ; R. Zhang
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- p. 735 –738 (4)
  A correlation-inheriting vector quantisation (VQ) image coding algorithm is presented to re-encode the output indices of VQ after analysing the correlation inheritance of the indices' neighbourhood. Simulation results indicate that this algorithm can compact the VQ index to achieve an ∼21:1 compression ratio on average. In accordance with this new algorithm, an efficient very large scale integration architecture is also derived that, after synthesis, achieves a system clock rate of 110 MHz using a 0.35 µm complementary metal-oxide-semiconductor standard library.
Field programmable gate array based parallel matrix multiplier for 3D affine transformations
- Author(s): F. Bensaali and A. Amira
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- p. 739 –746 (8)
  3D graphics performance is increasing faster than any other computing application. Almost all PC systems now include 3D graphics accelerators for games, computer aided design or visualisation applications. This article investigates the suitability of field programmable gate array devices as an accelerator for implementing 3D affine transformations. Proposed solution based on processing large matrix multiplication have been implemented, for large 3D models, on the RC1000 Celoxica board based development platform using Handel-C. Outstanding results have been obtained for the acceleration of 3D transformations using fixed and floating-point arithmetic.
Re-scalable V-BLAST MIMO system for FPGA
- Author(s): M.A. McKeown ; I.A.B. Lindsay ; D.G.M. Cruickshank ; J.S. Thompson ; S.A. Farson ; Y. Hu
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- p. 747 –753 (7)
  The development of a re-scalable hardware implementation of a V-BLAST (Vertical Bell Labs Space–Time) multiple input multiple output system for future wireless communications systems is described. Re-scalability will support rapid prototyping of such systems. A floating-point model of the re-scalable system is constructed to guide the development of a fixed-point model, and subsequently a re-scalable hardware implementation. The system uses the Gauss–Jordan elimination method to perform channel matrix inversion and altering the division-by-zero threshold in this matrix inversion process is shown to have a significant effect on bit error rate performance results. The re-scalable hardware implementation is described in a hardware description language in the form of an intellectual property block and several V-BLAST systems are synthesised onto field programmable gate arrays.

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IEE Proceedings - Vision, Image and Signal Processing

Volumes & issues:

Volume 153 (2006)

Volume 152 (2005)

Volume 151 (2004)

Volume 150 (2003)

Volume 149 (2002)

Volume 148 (2001)

Volume 147 (2000)

Volume 146 (1999)

Volume 145 (1998)

Volume 144 (1997)

Volume 143 (1996)

Volume 142 (1995)

Volume 141 (1994)

Latest content

Area efficient FIR filters for high speed FPGA implementation

Framework for FPGA-based discrete biorthogonal wavelet transforms implementation

Effective correlation vector quantisation algorithm and its VLSI architecture

Field programmable gate array based parallel matrix multiplier for 3D affine transformations

Re-scalable V-BLAST MIMO system for FPGA

Most viewed content for this Journal

Most cited content for this Journal