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Volume 153
Issue 2
IEE Proceedings - Computers and Digital Techniques
Volume 153, Issue 2, March 2006
Volumes & issues:
Volume 153, Issue 2
March 2006
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- Author(s): D. Shang ; F. Burns ; A. Bystrov ; A. Koelmans ; D. Sokolov ; A. Yakovlev
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 153, Issue 2, p. 71 –77
- DOI: 10.1049/ip-cdt:20050088
- Type: Article
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p.
71
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The authors present a novel circuit implementation of the advanced encryption standard using self-timed dual-rail technology. The design reduces leakage of internal information through balanced power consumption, which is achieved by avoidance of glitches and by data-independent switching behaviour. The design utilises a pipeline structure with built-in controllers and novel, highly balanced security latches. - Author(s): W.-T. Hsieh ; C.-C. Shiue ; C.-N.J. Liu
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 153, Issue 2, p. 78 –86
- DOI: 10.1049/ip-cdt:20045147
- Type: Article
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p.
78
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(9)
Building complex digital circuit power models is a popular approach for estimating the average power consumption without detailed circuit information. In the literature, most power models must increase in complexity to meet the accuracy requirement. The authors propose a novel power model for complementary metal-oxide-semiconductor sequential circuits using recurrent neural networks to learn the relationship between the input/output signal statistics and the corresponding average power dissipation. The complexity of our neural power model has almost no relationship to the circuit size and the number of inputs, outputs and flip-flops such that this power model can be kept very small, even for complex circuits. Using such a simple structure, the neural power models can still have high accuracy because they can automatically consider the non-linear power distribution characteristics and temporal correlation of the input sequences. The experimental results have shown that the estimations are still accurate with smaller variations even for short sequences with only 50 pattern pairs. - Author(s): I. Gonzalez and F.J. Gomez-Arribas
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 153, Issue 2, p. 87 –92
- DOI: 10.1049/ip-cdt:20050131
- Type: Article
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p.
87
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The authors present different alternatives to increase the performance of ciphering algorithms in embedded systems based on MicroBlaze, a soft-core processor especially designed for Xilinx field programmable gate arrays. Several implementations of the most usual cryptographic algorithms have been developed for comparison purposes. The architectural options offered by MicroBlaze, together with the different choices to connect custom-accelerating cores, are considered. Without a great design effort, an improvement reaching two orders of magnitude over all-software solutions could be obtained. - Author(s): C.-G. Lyuh and T. Kim
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 153, Issue 2, p. 93 –100
- DOI: 10.1049/ip-cdt:20050029
- Type: Article
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p.
93
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(8)
In deep-submicron technology, minimising the propagation delay and power consumption on buses is the most important design objective in system-on-chip design. In particular, the coupling effects between wires on the bus that can cause serious problems such as crosstalk delay, noise and power consumption. Most of the previous work on bus encoding targeted either (1) minimising the power consumption on bus, (2) minimising the crosstalk delay, or (3) exploiting the known probabilistic information of data, but not all of them. The authors propose a new bus-encoding algorithm that not only minimises the dynamic power consumption on bus but also eliminates the crosstalk delay. The authors achieve the combined objective of (1) and (2) by analysing, formulating and solving the problem of minimising a weighted sum of the self-transition and cross-coupled transition activities on bus in the context of the concept of self-shield encoding. From experiments using a set of benchmark designs, it is shown that the proposed encoding technique consumes 15.4–47.4% less power than existing techniques while totally eliminating the crosstalk delay. - Author(s): Z. Khan ; T. Arslan ; A.T. Erdogan
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 153, Issue 2, p. 101 –108
- DOI: 10.1049/ip-cdt:20050152
- Type: Article
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p.
101
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Inter-wire coupling is a major source of wire load and delay faults for on-chip buses implemented in ultra-deep submicron system on chip (SoC) systems. Elimination or minimisation of such faults is crucial to the performance and reliability of SoC designs. A novel on-chip bus encoding scheme targeting high-performance generic SoC systems is presented. In addition to its efficiency in terms of power, the scheme reduces delay faults by completely eliminating the most critical type of crosstalk coupled switched capacitance. The authors describe the technique and its implementation (using the widely adopted AMBA-AHB SoC bus standard) and provide experimental results indicating 22–36% energy saving for systems implemented in 0.18 µm CMOS technology. - Author(s): H. Rahaman and D.K. Das
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 153, Issue 2, p. 109 –116
- DOI: 10.1049/ip-cdt:20050079
- Type: Article
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p.
109
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A testable design for detecting stuck-at and bridging faults in programmable logic arrays (PLAs) based on double fixed-polarity Reed–Muller (DFPRM) expression is presented. DFPRM expression has the advantage of compactness and easy testability. The EXOR part in the proposed structure is designed as a tree of depth (⌈log2s⌉+1), where s is the number of product terms and sum terms in the given DFPRM expression realised by PLAs. This solves an open problem of designing an EXOR-tree-based RMC network that admits a universal test set. For an n-variable function, a test sequence of length (2n+8) vectors is sufficient to detect all single stuck-at and bridging faults in the proposed design. The proposed EXOR-tree-based network reduces circuit delay significantly compared with cascaded EXOR-based design. The test sequence is independent of the function and the circuit-under-test, and the test set can be stored in a ROM for built-in-self-test. - Author(s): J.-T. Yan
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 153, Issue 2, p. 117 –129
- DOI: 10.1049/ip-cdt:20050186
- Type: Article
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p.
117
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As the complexity of very large scale integration (VLSI) circuits increases, the routability problem becomes more and more important in modern VLSI design. In general, the flexibility improvement of the edges in a routing tree has been exploited to release the routing congestion and increase the routability in the routing stage. On the basis of the definition of the dynamic routing flexibility in a routing tree and the timing-constrained location flexibility of any Steiner point, an efficient assignment approach is proposed to reconstruct a timing-constrained flexibility-driven routing tree in a grid-based routing model by reassigning the feasible locations of the Steiner points in a routing tree. By using the concept of dynamic tree reconstruction, all the routing trees in a routing plane can be reconstructed tree by tree to release the possible congestion condition for timing-constrained congestion-driven global routing. The experimental results show that the proposed algorithm, TCGR_DTR, uses less time to obtain nearly 100% congestion improvement than the previously proposed algorithm, TCGR, for the tested benchmark circuits. - Author(s): J. Choi and H. Cha
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 153, Issue 2, p. 130 –136
- DOI: 10.1049/ip-cdt:20050031
- Type: Article
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p.
130
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As the computing environments are continuously moving towards battery-operated mobile and handheld systems, the development of energy-saving mechanisms for such devices has recently become a technical challenge. Dynamic voltage scaling (DVS) has historically been considered an effective method to reduce the processor power consumption. Conventional DVS techniques typically consider only processor utilisation issues in a policy-making process. However, as memory-bound multimedia applications are becoming popular in handheld devices, the DVS policies should consider the so-called ‘memory wall’ problem to maximise energy gain. Recent DVS techniques suffer from the inefficiency of their policies caused by the memory-wall problem while executing multimedia applications, and no previous research on DVS considers the problem explicitly. The existence of the memory wall problem in a real system is revealed and a metric that can be used to detect the problem in advance is found. A memory-aware DVS (M-DVS) technique that takes the memory wall problem fully into consideration is proposed. The experimental results on a PDA show that M-DVS can reduce ∼8% of additional power consumption, compared with conventional DVS, without any QoS degradation for handling multimedia clips.
High-security asynchronous circuit implementation of AES
Efficient power modelling approach of sequential circuits using recurrent neural networks
Ciphering algorithms in MicroBlaze-based embedded systems
Low-power bus encoding with crosstalk delay elimination
Low power system on chip bus encoding scheme with crosstalk noise reduction capability
Universal test set for detecting stuck-at and bridging faults in double fixed-polarity Reed–Muller programmable logic arrays
Dynamic tree reconstruction with application to timing-constrained congestion-driven global routing
Memory-aware dynamic voltage scaling for multimedia applications
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