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Volume 151
Issue 3
IEE Proceedings - Computers and Digital Techniques
Volume 151, Issue 3, May 2004
Volumes & issues:
Volume 151, Issue 3
May 2004
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- Author(s): C. Drosos ; L. Bisdounis ; D. Metafas ; S. Blionas ; A. Tatsaki ; G. Papadopoulos
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 151, Issue 3, p. 173 –182
- DOI: 10.1049/ip-cdt:20040496
- Type: Article
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p.
173
–182
(10)
The implementation and validation of a 5-GHz wireless LAN modem based on the HIPERLAN/2 standard is presented. In modern wireless communication systems, there is a demand for higher flexibility and more computational efficiency. Therefore the emphasis of this work is on the hardware–software structure of the developed modem and its processes, in order to offer a good balance of these requirements. In order to efficiently design and validate the behaviour of the modem, a behavioural model was developed in UML (Unified Modelling Language) as a part of the overall HIPERLAN/2 system's model. The processes of the modem were implemented in an instruction-set processor and custom hardware, combining the advantages of both software and hardware implementations. The communication between the software and hardware parts of the modem is achieved through a specialised programmable interface unit. The UML-based model of the actual HIPERLAN/2 system is used in order to validate the modem's behaviour, using scenarios from in-field usage (such as transfer of data using FTP or HTTP). Furthermore, the validation of the algorithms implemented within the modem was based on this system model, and performed through the use of a custom-validation framework. This framework produces patterns for the validation of the modem's algorithms, at three different development phases (algorithmic, HDL, FPGA-based prototyping), derived from the simulation of the system model in a consistent and automatic way. Implementation figures and co-simulation results for the developed wireless LAN modem are also given. - Author(s): A. Abbasian ; S.H. Rasouli ; A. Afzali-Kusha ; M. Nourani
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 151, Issue 3, p. 183 –190
- DOI: 10.1049/ip-cdt:20040256
- Type: Article
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p.
183
–190
(8)
A logic family called no-race charge-recycling complementary pass transistor logic (NCRCPL) is proposed. The use of a new regenerator in NCRCPL leads to a complete elimination of the controller in the circuit hence reducing the number of transistors and power consumption. It has an additional benefit of reduced sensitivity to signal skew. The proposed logic family in its modular structure also has a better performance than previous modular structures based on charge recycling. Furthermore, a latch structure called dual-rail isolated latch which can be used for pipelining NCRCPL has been proposed. The new latch had a much better performance compared with previous static latch structures. To enhance the power efficiency of the pipeline configuration an event-detector circuit is proposed that may reduce the power consumption by up to 50% compared with previous pipeline configurations. To assess the performance improvements of the logic structures of this work compared with other charge recycling logic structures, logic gates and ripple carry adders are studied. - Author(s): C. Chen ; R.-L. Chen ; M.-H. Sheu
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 151, Issue 3, p. 191 –198
- DOI: 10.1049/ip-cdt:20040258
- Type: Article
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p.
191
–198
(8)
Conventional additive normalisation methods suffer from their linear convergence rate. A new method yields the normalisation factor values directly from predetermined terms without computation. The number of normalisation factors obtained in each normalisation stage is twice the number of normalisation factors in the previous stage. As a result the number of normalisation stages needed to compute the exponential function is proportional to the logarithmic value of the operand word-length. In other words, the convergence rate of the proposed method is exponential. These two advantages of the new method significantly enhance the speed of the additive normalisation method. Based on this method, 24-bit and 53-bit exponential unit architectures have been designed. Extensive 24-bit unit simulations verify the proposed algorithm and error analysis method. Based on the analysis, the hardware cost of the 53-bit unit includes 80 kbits ROM, four adders, and four multipliers. - Author(s): P.S. Roop ; A. Sowmya ; S. Ramesh ; H.-F. Guo
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 151, Issue 3, p. 199 –208
- DOI: 10.1049/ip-cdt:20040502
- Type: Article
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p.
199
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(10)
Automatic IP (intellectual property) matching is a key to the reuse of IP cores. A new tabled logic programming-based IP matching algorithm is given that can check whether a given programmable IP can be adapted to match a given specification. When such adaptation is possible, the algorithm also generates a device driver (an interface) to adapt the IP. Though simulation, refinement and bisimulation algorithms exist, they cannot be used to check the adaptability of an IP, which is the essence of reuse. The IP matching algorithm is based on a formal verification technique called forced simulation. A forced simulation matching algorithm is implemented using a tabled logic programming environment, which provides distinct advantages for encoding such an algorithm. The tool has been used to match several specifications to programmable IPs, achieving on an average 12 times speedup and 64% reduction in code size in comparison with previously published algorithms. - Author(s): D. Shang ; F. Burns ; A. Koelmans ; A. Yakovlev ; F. Xia
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 151, Issue 3, p. 209 –220
- DOI: 10.1049/ip-cdt:20040525
- Type: Article
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p.
209
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(12)
A technique is proposed to synthesise system behavioural specifications written in VHDL into speed-independent asynchronous circuits constructed using David cells. This technique combines the advantages of logic synthesis and syntax-directed translation techniques. Coloured Petri nets and labelled Petri nets are used as intermediate formats for datapath and control representation. Speed-independent asynchronous circuits are obtained from these nets via direct translation. Several examples demonstrate the viability of the technique, which produces superior results compared with other ones. - Author(s): B.J. Falkowski
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 151, Issue 3, p. 221 –230
- DOI: 10.1049/ip-cdt:20040257
- Type: Article
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p.
221
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(10)
Various representations of logic functions are frequently used in development of computer-aided design tools for VLSI digital circuits. Selected different compact representations of logic functions and their spectra are presented for the first time in lossless compression of grey-scale images. After coding of intensities, a prediction process is performed followed by the mapping of prediction residuals that are split into bit-planes to which the compression technique is applied. The planes can be coded as uncompressed or compressed using variable block-size segmentation and coding. The coding and compression schemes used include various compact representations of logic functions such as: minterm coding, co-ordinate data coding, discrete multiple-valued input binary functions, basic Walsh, triangular, Reed–Muller weights and spectra and the reference row technique. Experimental results indicate that the technique is efficient when compared with other methods. - Author(s): L. Harn ; C.-Y. Lin ; T.-C. Wu
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 151, Issue 3, p. 231 –234
- DOI: 10.1049/ip-cdt:20040247
- Type: Article
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p.
231
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(4)
A structured multisignature scheme is an order-sensitive multisignature scheme that allows participating signers to sign messages in compliance with a specified signing order. It has been shown that the Burmester et al. order-sensitive multisignature scheme cannot prevent all signers producing a valid multisignature without following the specified signing order. The paper proposes two structured multisignature algorithms, one based on the RSA scheme and the other on an ElGamal-type scheme. Incorporation of both order-free and order-sensitive multisignature algorithms together is shown to construct a generalised multisignature algorithm. - Author(s): I. Polian ; I. Pomeranz ; S.M. Reddy ; B. Becker
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 151, Issue 3, p. 235 –244
- DOI: 10.1049/ip-cdt:20040141
- Type: Article
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p.
235
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(10)
The size of an n-detection test set increases approximately linearly with n. This increase in size may be too fast when an upper bound on test set size must be satisfied. A test generation method is proposed for obtaining a more gradual increase in the sizes of n-detection test sets, while still ensuring that every additional test would be useful in improving the test set quality. The method is based on the use of fault-dominance relations to identify a small subset of faults (called maximally dominating faults) whose numbers of detections are likely to have a high impact on the defect coverage of the test set. Structural analysis obtains a superset of the maximally dominating fault set. A method is proposed for determining exact sets of maximally dominating faults. New types of n-detection test sets are based on the approximate and exact sets of maximally dominating faults. The test sets are called (n,n2)-detection test sets and (n,n2,n3)-detection test sets. Experimental results demonstrate the usefulness of these test sets in producing high-quality n-detection test sets for the combinational logic of ISCAS-89 benchmark circuits. - Author(s): T.-H. Tsai and Y.-C. Yang
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 151, Issue 3, p. 245 –251
- DOI: 10.1049/ip-cdt:20040486
- Type: Article
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p.
245
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(7)
An optimised approach to MPEG layer-3 (MP3) audio decoding is presented, with the main theme focused on the synthesis subband. Since the synthesis subband is the most power-consuming component in decoding, a cost-effective architecture is proposed based on a system-design consideration. By means of an algorithm and architecture, the synthesis subband achieves a high throughput with reduced memory requirements and hardware complexity. With a two-stage pipeline architecture, it allows 100% hardware utilisation and is suitable for low-power implementation. In addition, the chip design in a 0.35 μm process is also accomplished. It occupies a die area of about 2.7 × 3.2 mm2 with a transistor count of 157469 and a low-power dissipation of only 2.92 mW. - Author(s): D.J.D. Milton ; A.D. Brown ; M. Zwolinski ; P.R. Wilson
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 151, Issue 3, p. 252 –264
- DOI: 10.1049/ip-cdt:20040241
- Type: Article
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p.
252
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(13)
Behavioural synthesis is the process whereby the description of a system behaviour is automatically translated into a physical implementation of that system. An essential prerequisite of this process is a language in which to express the design. Traditionally, hardware description languages (HDLs) are used for this, but there is currently much interest in the idea of coercing conventional software languages to do the same job (SystemC is the most prominent example of this). The goal of the research described is to increase the synthesisable description space to support the description of systems utilising dynamic allocation. VHDL supports the concepts of dynamic allocation, and is used as the entry language for the system, although without loss of validity SystemC could have been used. How the structures conventionally associated with dynamic description are implemented and supported is described together with a heap management subsystem that is both space and speed-efficient and which communicates with the user's design via an automatically generated interface.
Hardware–software design and validation framework for wireless LAN modems
No-race charge-recycling complementary pass transistor logic
Fast additive normalisation method for exponential computation
Tabled logic programming based IP matching tool using forced simulation
Asynchronous system synthesis based on direct mapping using VHDL and Petri nets
Compact representations of logic functions for lossless compression of grey-scale images
Structured multisignature algorithms
Exact computation of maximally dominating faults and its application to n-detection tests for full-scan circuits
Low power and cost effective VLSI design for an MP3 audio decoder using an optimised synthesis-subband approach
Behavioural synthesis utilising dynamic memory constructs
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