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Volume 150
Issue 3
IEE Proceedings - Computers and Digital Techniques
Volume 150, Issue 3, May 2003
Volumes & issues:
Volume 150, Issue 3
May 2003
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- Author(s): C. Gopalakrishnan ; S. Katkoori ; S. Gupta
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 150, Issue 3, p. 133 –142
- DOI: 10.1049/ip-cdt:20030418
- Type: Article
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p.
133
–142
(10)
An approach is presented for power minimisation of CMOS combinational circuits based on transforming power-expensive inputs to functionally equivalent low-power inputs. It is assumed that the environment information is available in the form of either word-level statistics or a long representative input sequence. From the environment information, power-efficient input transformations are derived that will save power for any input stream that satisfies the environment properties. A transform module is synthesised that is prepended to the primary inputs of the module. The proposed approach can be applied at the system level by propagating environment information to the primary outputs of the system and then deriving transform circuits for each module. As an example of real-world application, results are presented for a DCT module in a JPEG compression chip with different input environments (e.g. face recognition dataset and weather forecasting). Experimental results are highly encouraging. - Author(s): D. Kania
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 150, Issue 3, p. 143 –149
- DOI: 10.1049/ip-cdt:20030223
- Type: Article
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p.
143
–149
(7)
An efficient approach to logic synthesis of multioutput functions using PAL-based devices is proposed. According to this approach, product terms included in a logic block can be shared by several functions. The method consists of a search for the common multioutput implicants. After completion of two-level minimisation of the multioutput function, the process of searching for the common implicants is carried out. An algorithm has been implemented within the PAL decomposition system. The results are compared with classical technology mapping and a synthesis of benchmarks executed by means of firmware. - Author(s): S.R. Naidu
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 150, Issue 3, p. 150 –156
- DOI: 10.1049/ip-cdt:20030420
- Type: Article
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p.
150
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(7)
A fast polynomial-time algorithm was recently proposed to determine whether a logic function expressed as a unate DNF (disjunctive normal form) can be expressed as a read-once formula where each variable appears no more than once. The paper uses a combinatorial characterisation of read-once formulas to achieve its objective. It is shown that one can use the well-known and more intuitive notion of algebraic factoring to devise a recognition algorithm for read-once formulas of slightly worse complexity than the best known polynomial-time algorithm for this problem. - Author(s): H.R. Simpson
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 150, Issue 3, p. 157 –182
- DOI: 10.1049/ip-cdt:20030419
- Type: Article
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p.
157
–182
(26)
The timing effects of interactions between the component concurrent processes of a real-time system, and between these processes and the system environment, have a crucially important role to play in determining the temporal properties of the system as a whole. First, a new and comprehensive set of unidirectional protocols for characterisation of these timing effects is developed, based on interaction by means of data items shared between two processes. Each protocol is represented by a graphical symbol which denotes its functional and temporal properties, and axiomatic specifications for the protocols are derived which define and reveal their essential behaviour. The protocol set is then extended to include important bidirectional forms to allow for the remoting of interfaces, which is needed in distributed systems, and to support remote procedure call techniques. Protocol implementation takes the form of a connector known as a route. It is shown how routes can be combined and encapsulated within higher level constructs to give distributed interaction, and a sample algorithmic implementation of a route is given. The axiomatic specification technique is used to make comparisons with some more conventional forms of interaction. The paper brings new insights to the characterisation and realisation of connectors in distributed real-time systems. - Author(s): S. Roy ; U. Maulik ; S. Bandyopadhyay ; S. Basu ; B.K. Sikdar
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 150, Issue 3, p. 183 –188
- DOI: 10.1049/ip-cdt:20030421
- Type: Article
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p.
183
–188
(6)
BIST design for sequential circuits is a difficult enterprise. The difficulty stems from the lack of uniformity in reachability and emitability of machine states. The paper introduces a BIST-quality metric termed the FiF-FoF (fan-in-factor and fan-out-factor) defined on FSM-states. Based on the FiF-FoF analysis, an efficient synthesis scheme is presented that ensures all state codes of FSM may appear with uniform likelihood at the present state lines during the test phase. The uniform mobility of states ensures higher fault efficiency in a BIST structure of the circuit. Extensive experimentation on MCNC benchmarks and randomly generated large FSMs shows that the proposed scheme improves the fault efficiency of sequential circuits significantly, with marginal area overhead.
Power optimisation of combinational circuits by input transformations
Efficient approach to synthesis of multioutput boolean functions on PAL-based devices
Algebraic factoring algorithm to recognise read-once functions
Protocols for process interaction
Fan-in- and fan-out-factor oriented BIST design for sequential machines
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