Home
>
Journals & magazines
>
IEE Proceedings - Computers and Digital Technique...
>
Volume 149
Issue 5
IEE Proceedings - Computers and Digital Techniques
Volume 149, Issue 5, September 2002
Volumes & issues:
Volume 149, Issue 5
September 2002
-
- Author(s): B.A. Izadi and F. Özgüner
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 149, Issue 5, p. 197 –202
- DOI: 10.1049/ip-cdt:20020720
- Type: Article
- + Show details - Hide details
-
p.
197
–202
(6)
A real-time fault-tolerant design for a d-dimensional hypercube multiprocessor with two modes of operation is presented and its reconfigurability is examined. The augmented hypercube, at stage one, has a spare node connected to each node of a subcube of dimension i, and the spare nodes are also connected as a (d−i)-dimensional hypercube. At stage two, the process is repeated by assigning one spare node to each (d−i−j)-dimensional spare subcube of stage one. Two modes of operations are considered, one under heavy computation or hard deadline and the other under light computation or soft deadline. By utilising the capabilities of wave-switching communication modules of the spare nodes, faulty nodes and faulty links can be tolerated. Both theoretical and experimental results are presented. Compared with other proposed schemes, the proposed approach can tolerate significantly more faulty components with a low overhead and no performance degradation. - Author(s): L. Wang and A.E.A. Almaini
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 149, Issue 5, p. 203 –212
- DOI: 10.1049/ip-cdt:20020674
- Type: Article
- + Show details - Hide details
-
p.
203
–212
(10)
The properties of the polarity for sum-of-products (SOP) expressions of Boolean functions are formally investigated. A transform matrix S is developed to convert SOP expressions from one polarity to another polarity. It is shown that the effect of SOP polarity is to reorder the on-set minterms of a Boolean function. Furthermore, the transform matrix P for fixed polarity Reed-Muller (FPRM) expressions for the conversion between two different polarities, based on the properties of SOP polarity, is achieved. Comparison of these two matrices shows that the Reed-Muller transform matrix P has a much more complex structure. Additionally, the best polarity of FPRM forms with the least on-set terms corresponds with the polarity of SOP forms with the best ‘order’ of the on-set minterms. Applying these algebraic properties of the transform matrix P, a fast algorithm is presented to obtain the best polarity of FPRM expressions for large multiple output Boolean functions. The computation time is independent of the number of outputs. The developed program is tested on common personal computers and the results for benchmark examples of up to 25 inputs and 29 outputs are presented. - Author(s): J.-F. Tu and L.-H. Wang
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 149, Issue 5, p. 213 –218
- DOI: 10.1049/ip-cdt:20020426
- Type: Article
- + Show details - Hide details
-
p.
213
–218
(6)
Multi-threading is one of the methods of improving the performance of processors. In this paper, a super-multi-threaded processor is proposed. In the multi-threaded architecture, a thread dispatcher is constructed to manage the thread-level parallelism and instruction-level parallelism, and to build a communication unit to transfer the dependence data among the threads. Furthermore, the authors illustrate the control flow with a Petri net model, and simulate the proposed architecture using a trace-driven simulation tool suit. From the simulation results, the authors find that the proposed architecture achieves two goals: the individual thread slot in the proposed multi-threaded processor achieves more significant throughput gains than the DLX pipeline processor, and it minimises the cost of the expansion of multi-threaded processor systems. - Author(s): P.R. Rao and I. Chakrabarti
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 149, Issue 5, p. 219 –228
- DOI: 10.1049/ip-cdt:20020427
- Type: Article
- + Show details - Hide details
-
p.
219
–228
(10)
Although the full radix-4 CORDIC algorithm is efficient compared to the standard radix-2 version, the scale-factor overhead causes its improvement to be limited. In this work, an algorithm and its associated architecture have been proposed for parallel compensation of the scale factor for the radix-4 CORDIC algorithm in the rotation mode. The proposed method, which makes no prior assumptions about the elementary angles of rotation, reduces the latency from n to (n/2)+3, where n is the precision length in bits, at the cost of a reasonable increase in hardware complexity. The architecture presented relates to the redundant signed-digit number system. The architecture has been modelled in VHDL and simulated to establish its functional validity. - Author(s): P.N. Swamy ; I. Chakrabarti ; D. Ghosh
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 149, Issue 5, p. 229 –239
- DOI: 10.1049/ip-cdt:20020428
- Type: Article
- + Show details - Hide details
-
p.
229
–239
(11)
The realisation of a real-time video-coding system calls for a dedicated motion-estimation architecture. Whereas all the existing motion-estimation architectures offer either computational speed or hardware simplicity, in this paper, the authors propose an efficient pipelined parallel architecture for the one-dimensional hierarchical search (1DHS) block-matching algorithm that is efficient in terms of both speed and hardware cost. The architecture exploits the advantageous features of the 1DHS algorithm and makes use of an intelligent memory configuration to achieve high speed while keeping the hardware complexity low. The architecture also makes use of a data-reuse technique, thereby reducing the number of external memory accesses. The proposed architecture has been modelled in VHDL and simulated to establish its functional validity. - Author(s): S.M. Ngwira and P. Tshabalala
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 149, Issue 5, p. 240 –244
- DOI: 10.1049/ip-cdt:20020405
- Type: Article
- + Show details - Hide details
-
p.
240
–244
(5)
An artificial neural network analysis is presented to predict the input variable subsets that give efficient disjunctive decompositions of complex combinatorial logic functions. The subsets obtained match substantially with the optimum orderings from an exhaustive search for disjunctive decompositions. The subsets reveal significantly scaled down numbers of orderings in the search domain. The technique can thus serve as a pre-processor of comprehensive exhaustive search algorithms.
Real-time fault-tolerant hypercube multicomputer
Exact minimisation of large multiple output FPRM functions
SMTA: next-generation high-performance multi-threaded processor
High-performance compensation technique for the radix-4 CORDIC algorithm
Architecture for motion estimation using the one-dimensional hierarchical search block-matching algorithm
Neural network analysis for the identification of optimal variable orderings in the decomposition of complex logic functions
Most viewed content for this Journal
Article
content/journals/ip-cdt
Journal
5
Most cited content for this Journal
We currently have no most cited data available for this content.