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Volume 149
Issue 1
IEE Proceedings - Computers and Digital Techniques
Volume 149, Issue 1, January 2002
Volumes & issues:
Volume 149, Issue 1
January 2002
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- Author(s): S–C Chang ; D. I. Cheng ; C–W Yeh
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 149, Issue 1, p. 1 –8
- DOI: 10.1049/ip-cdt:20020160
- Type: Article
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Redundancy removal is an important step in combinational logic optimisation. After a redundant wire is removed, other originally redundant wires may become irredundant, and some originally irredundant wires may become redundant. When multiple redundancies exist in a circuit, this creates a problem where we need to decide which redundancy to remove first. The authors present both a theoretical analysis and a very efficient heuristic to deal with multiple redundancies. Each redundant wire is associated with a Boolean function that describes how the wire can remain redundant after removing other wires. When multiple redundancies exist, this set of Boolean functions characterises the global relationship among redundancies. The proposed heuristic for dealing with the multiple-redundancy problem is very efficient and the experimental results are very promising. - Author(s): Y. Son ; J. Chong ; G. Russell
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 149, Issue 1, p. 9 –15
- DOI: 10.1049/ip-cdt:20020158
- Type: Article
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A new built-in self-test architecture, E-BIST, suitable for a test-per-clock scheme, is proposed. The E-BIST architecture is based on STUMPS, which uses a linear feedback shift register (LFSR) as the test generator, a multiple input shift register (MISR) as the response compactor, and shift register latch (SRL) channels as multiple scan paths. In E-BIST a degenerate MISR structure is used for every SRL channel; this offers reduced area overheads and has less impact on performance than the STUMPS technique. It is also shown that the masking probability of the proposed SRL channel structure is 21−(N+L), where N and L are the number of test patterns and the length of the SRL channel, respectively. Results of the experiments on ISCAS 89 benchmark circuits show that this architecture is also suitable for robustly detecting path delay faults, with improved fault coverage, when the Hamming distance of the data in the SRL channel is considered. - Author(s): A. Amira ; A. Bouridane ; P. Milligan ; A. Belatreche
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 149, Issue 1, p. 17 –24
- DOI: 10.1049/ip-cdt:20020159
- Type: Article
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Discrete orthogonal transforms (DOTs) are important in many applications, including image and signal processing. Novel 1D and 2D bit-level systolic architectures are presented for the efficient implementation of DOTs for image and signal processing. The authors describe the design methodology of the techniques based on the Baugh–Wooley algorithm, and the associated design including a case study of an FPGA implementation. They also discuss the efficiency of implementations which have O(N 2) and O(2nN) as the area and time complexities for 2D structures, respectively, and O(N) and O(2nN) as the area and time complexities for 1D structures, respectively (where N is the transform length and n is the word length). Furthermore, it is shown that the architectures are parameterisable and that the area required by the designs can be predicted for different values of N and n. A comparison with existing and similar structures has shown that the proposed architectures perform better. - Author(s): K. Lin and C.-P. Chung
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 149, Issue 1, p. 25 –31
- DOI: 10.1049/ip-cdt:20020157
- Type: Article
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Dictionary-based code compression stores the most frequently used instruction sequences in a dictionary, and replaces the occurrences of these sequences in the program with codewords. The large dictionary size is due mainly to many instruction sequences which are different only in operands, but are otherwise the same. The operand factorisation technique divides the expression tree into tree-pattern (opcode sequence) and operand-pattern (operand sequence) to reduce this redundancy; instruction sequences with the same opcodes but different operands may thus share the same tree-pattern dictionary entry. The paper proposes an operand field remapping method to further reduce dictionary size. The key idea is to explore the relations between the current operand to be compressed with those already compressed. The operand-pattern dictionary is therefore divided into an operand remapping dictionary and an operand list dictionary. Each entry in the operand remapping dictionary indicates whether the operand (register or immediate value) to be compressed is the most used operand, the same as the destination register of the previous instructions, or otherwise. With this remapping technique, the operand dictionary size is greatly reduced. An average 46% compression ratio can be achieved where compression ratio=(dictionary size+compressed code size)/(original program size).
Removing multiple redundancies in combinational circuits
E-BIST: enhanced test-per-clock BIST architecture
Design of efficient architectures for discrete orthogonal transforms using bit level systolic structures
Code compression techniques using operand field remapping
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