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Volume 148
Issue 6
IEE Proceedings - Computers and Digital Techniques
Volume 148, Issue 6, November 2001
Volumes & issues:
Volume 148, Issue 6
November 2001
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- Author(s): J.L. Imaña and J.M. Sánchez
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 148, Issue 6, p. 189 –195
- DOI: 10.1049/ip-cdt:20010706
- Type: Article
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p.
189
–195
(7)
Boolean or switching equations are powerful mathematical tools for digital logic. Several problems in digital circuit design, such as automatic test pattern generation, could be efficiently solved if fast procedures for solving Boolean equations were available. Several methods for solving this class of equations have been developed, but their efficiency is a problem. A new formulation for the computation of Boolean operations based on cubic representation of Boolean functions, termed the cube set method, is presented. The solutions provided by this approach are given as a set of cubes satisfying the disjoint property. Some definitions and theorems are given to describe the method and experimental results are presented. - Author(s): D. Chen ; T. Aoki ; N. Homma ; T. Higuchi
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 148, Issue 6, p. 196 –206
- DOI: 10.1049/ip-cdt:20010725
- Type: Article
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p.
196
–206
(11)
To characterise and analyse the performance of evolutionary graph generation (EGG) on a cluster of PCs, a parallel version of the EGG system, called the distributed EGG (DEGG) system, has been developed using a message-passing interface (MPI). To demonstrate the capability of DEGG, it is applied to find the optimal design of various multipliers. Experimental results substantially clarify that the DEGG system consistently performs better than the EGG system. Moreover, the ability and solution quality of the DEGG system's search can be further enhanced by the use of the self-adaptation mechanism of operator probabilities. - Author(s): S.-M. Yen
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 148, Issue 6, p. 207 –213
- DOI: 10.1049/ip-cdt:20010743
- Type: Article
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p.
207
–213
(7)
A software-based prepaid micropayment scheme is developed. As with existing prepaid micropayment schemes, the profits of the merchants are protected. Furthermore, in this proposed scheme, fairness for the customers is also assured. More precisely, in this new scheme, the merchant, after receiving prepaid money, can only claim that a customer has already spent a specific amount of money by showing the required cryptographic witness which can only be received from that customer when making a payment. Most importantly, in this new scheme, no public key-signature computation is required. Finally, it will be shown that, owing to its simplicity and high performance, the proposed scheme can also be employed by small pieces of electronic equipment for general-purpose resource-access control. - Author(s): M. Ould-Khaoua and G. Min
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 148, Issue 6, p. 215 –219
- DOI: 10.1049/ip-cdt:20010789
- Type: Article
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p.
215
–219
(5)
Adding virtual channels to k-ary n-cubes can greatly improve network performance because they act as `bypass' lanes to reduce message blocking in the network. Although several analytical models have been proposed for circuit switching, most of these have not included the effects of virtual channel multiplexing on network performance. This paper presents a new performance model of circuit switching in k-ary n-cubes with virtual channels. The proposed model can capture the effects of the back-off period experienced by a message in the event of a connection failure. Results from simulation experiments confirm that the model exhibits a good degree of accuracy for various network sizes and under different operating conditions. - Author(s): W.F. Wallace ; S.S. Dlay ; O.R. Hinton
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 148, Issue 6, p. 221 –226
- DOI: 10.1049/ip-cdt:20010781
- Type: Article
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p.
221
–226
(6)
The paper presents a new type of simple adder, suitable for asynchronous digital circuits and implementation in VLSI technology, which has either speed and/or area advantages over existing designs. It is based on the concept of predicting the carry from least to most significant halves of a 32 or 64 bit adder in such a way that it has a high probability of being correct, while introducing only a low area overhead from the required early completion control circuitry. Detailed design and simulation of the adder at the gate level is presented, together with its evaluation by comparing detailed performance with equivalent ripple, carry lookahead, and carry select designs. Since the objective is improved asynchronous circuits, it is average rather than worst-case delays that are the significant measures. In comparison to other adder networks it is demonstrated that by using the important metrics of area, speed and delay–area product the proposed adder can outperform the 32 bit and 64 bit adders cited in the literature. Delay–area product results show that the proposed approach gives a saving of over 14% and 24% on the carry-select lookahead schemes for 32 bit and 64 bit adders respectively. - Author(s): T.-S. Chang and C.-W. Jen
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 148, Issue 6, p. 227 –232
- DOI: 10.1049/ip-cdt:20010726
- Type: Article
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p.
227
–232
(6)
With the increasing demand for video-signal processing and transmission, high-speed programmable FIR filters are required for real-time processing. This paper presents a hardware-efficient pipelined FIR architecture with programmable coefficients. FIR operations are first reformulated into multi-bit DA form at an algorithm level. Then, at the architecture level, the ( p, q) compressor, instead of Booth encoding or RAM implementation, is used for high-speed operation. Due to the simple architecture, we can easily pipeline the proposed FIR filter to the adder level and save up to half of the cost of previous designs without sacrificing performance. The presented design is useful for bit-parallel input design, which can save 36.7% of the area cost compared with previous approaches. - Author(s): Z. Shao
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 148, Issue 6, p. 233 –237
- DOI: 10.1049/ip-cdt:20010780
- Type: Article
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p.
233
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(5)
The paper proposes new cryptographic systems using a self-certified public key, including signature scheme, key distribution system and public key cryptosystem, the security of which is based on discrete logarithms. The public key and the identity of users can be verified implicitly at the same time as the cryptographic systems work. The proposed schemes require reduced computing time and increased storage. - Author(s): S. Roy ; S. Bandyopadhyay ; U. Maulik
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 148, Issue 6, p. 238 –244
- DOI: 10.1049/ip-cdt:20010723
- Type: Article
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p.
238
–244
(7)
The elimination of all complex triangles (CT) is an essential step in the rectangular dualisation approach of floor-planning. It is known that the weighted complex triangle elimination problem, i.e. the version of the problem where the input to the problem is a weighted adjacency graph, is NP-complete. Also, for adjacency graphs with 0-level containment the unweighted problem is optimally solvable in polynomial time. However, the complexity of the unweighted CTE problem for general graphs with multiple levels of containment was unknown though it was conjectured that this problem is also NP-complete. The authors present a claim that the unweighted complex triangle elimination problem for general graphs with multiple levels of containment is, indeed, NP-complete, and present a proof supporting the claim.
Formulation for the computation of Boolean operations
Pragmatic method for the design of fast constant-coefficient combinational multipliers
PayFair: a prepaid internet micropayment scheme ensuring customer fairness
Circuit switching: an analysis for k-ary n-cubes with virtual channels
Probabilistic carry state estimate for improved asynchronous adder performance
Hardware-efficient pipelined programmable FIR filter design
Cryptographic systems using a self-certified public key based on discrete logarithms
Proof regarding the NP-completeness of the unweighted complex-triangle elimination (CTE) problem for general adjacency graphs
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