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Volume 148
Issue 1
IEE Proceedings - Computers and Digital Techniques
Volume 148, Issue 1, January 2001
Volumes & issues:
Volume 148, Issue 1
January 2001
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- Author(s): C.-N. Liu and J.-Y. Jou
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 148, Issue 1, p. 1 –6
- DOI: 10.1049/ip-cdt:20010203
- Type: Article
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Simulation is still the primary approach for the functional verification of register-transfer level circuit descriptions written in hardware description language (HDL). The major problem of the simulation approach is to choose a good metric to gauge the quality of the test patterns. The finite state machine (FSM) coverage test can find most of the design errors in a FSM. However, it is impractical for large designs because of the state explosion problem. In the paper, a higher-level FSM model is proposed to replace the conventional FSM model in the coverage test. The state transition graph can be significantly reduced in the model so that the complexity of the test sets becomes acceptable, even for large designs. This higher-level FSM model, called the semantic finite state machine (SFSM) model, can be easily extracted from the original HDL code automatically with little computation overhead. The advantages of using this model instead of the conventional FSM model in HDL design validation are thoroughly discussed. The implementation results show that it is indeed a promising functional coverage metric. - Author(s): B.J. Falkowski and S. Rahardja
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 148, Issue 1, p. 7 –14
- DOI: 10.1049/ip-cdt:20010200
- Type: Article
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Properties of transformation matrices for multiple-valued-input binary-output PLI logic are discussed. It is shown that some of PLI logic transformations for Boolean functions are still applicable for multiple-valued-input binary functions with appropriate coding and new matrix functions. Fast algorithms of suitable PLI transformation matrices are shown and their complexity analysis is discussed. - Author(s): F. Buzluca and E. Harmancı
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 148, Issue 1, p. 15 –21
- DOI: 10.1049/ip-cdt:20010201
- Type: Article
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In a distributed system for hard real-time applications, communication by message exchange between tasks residing on different nodes must happen in bounded time. Due to its timed token MAC protocol, FDDI provides a suitable network structure for these systems. The paper proposes a synchronous bandwidth allocation (SBA) scheme for deadline guarantees of synchronous messages with arbitrary deadlines in an FDDI network. The major amount of information used by this scheme in calculating the synchronous bandwidth of a node is locally available to the node involved. The limited use of global data makes this scheme suitable for dynamic environments. In this study, a distributed management protocol has also been designed to update synchronous bandwidths of nodes dynamically when the data load in the network changes. It is shown that the scheme performs better than other previously published ‘pure’ local schemes. - Author(s): K. Kuusilinna ; V. Lahtinen ; T. Hämäläinen ; J. Saarinen
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 148, Issue 1, p. 23 –30
- DOI: 10.1049/ip-cdt:20010210
- Type: Article
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Finite state machine (FSM) optimisation has usually been studied through state assignment, state vector encoding, and combinational logic optimisation. Such details should not be consequential in behavioural descriptions. On the other hand, describing correct and efficient hardware structures in VHDL (VHSIC hardware description language), or generally in any high-level description language, is more a question of description style than correct language statements. Therefore, more or less conscious choices are made in the design description itself that guide the synthesis software toward a specific implementation. The best implementation is also dependent on the target technology and, therefore, there is no single best description style for all FSMs. The paper is a study of the kind of performance trade-offs that can be made by changing the description style. A program is shown to be able to generate these different descriptions from an intermediate format (kiss2) describing the FSM. Therefore, this process for finding a better description could be automated and performed by the synthesis software itself. Descriptions are tested on a set of 13 FSMs most from a benchmark suite LGSynth93. The results show at least two times better performance of speed or area in the best description compared with the worst. In performance critical applications this difference can be of a crucial importance. - Author(s): A.C. Williams ; A.D. Brown ; Z. Baidas
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 148, Issue 1, p. 31 –43
- DOI: 10.1049/ip-cdt:20010208
- Type: Article
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During behavioural synthesis, an abstract functional description of a system is mapped automatically onto a physical structure. In a competitive setting, this mapping is highly optimised (the data flow is re-arranged, units and registers are multiplexed and so on) to deliver a final structure that meets some overall user-supplied specification. Ultimately, however, the physical functional units are drawn from a predefined (human-designed) library; these may be thought of as the leaf-level modules in the design hierarchy. Design reuse and increasing sophistication of module libraries inevitably lead to leaf modules becoming larger and more complex. As these modules are, by definition, atomic, a synthesis system is unable to capitalise on any internal similarities the leaf modules may possess. The design, construction and effects of using a hierarchically defined module library are described in the paper. The set of leaf-level modules made available to the synthesis environment is conventional (add, subtract, multiply and so on), but the optimiser is capable of `ripping apart' these modules to manipulate their inner structures. Two advantages accrue from the technique: it is possible to optimise behavioural designs far more effectively, with up to a 65% reduction in area and a 46% reduction in delay; and it is possible to build library modules that have tightly controllable internal timing relationships. This is essential when designing systems that communicate externally via low-level protocols; behavioural synthesis, by its very nature, usually distorts timing information. Using the technique, it is possible to create `islands of fixed timing' embedded in the synthesised design. - Author(s): K.M. Martin and J. Nakahara
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 148, Issue 1, p. 45 –48
- DOI: 10.1049/ip-cdt:20010204
- Type: Article
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Threshold schemes are adaptable cryptographic primitives that distribute trust in secret data by requiring k out of n entities to co-operate before the data can be recovered. An important security management issue relating to threshold schemes is the problem of updating the parameters of a threshold scheme. The paper discusses serious shortcomings in two proposed protocols for threshold parameter update. - Author(s): N. Burgess
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 148, Issue 1, p. 49 –52
- DOI: 10.1049/ip-cdt:20010202
- Type: Article
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A new Chinese remainder theorem (CRT)-based technique for the conversion of numbers in residue number system (RNS) format to binary representation is proposed that employs a high-radix SRT division-like architecture. The major benefit of the new technique is that it permits the efficient conversion of residue numbers with many moduli. A k-modulus RNS converter returning a w-bit result employs a (⌈log2 k⌉+1)-bit carry–propagate adder, a ROM with ⌈log2 k⌉+3 address bits, a (w+⌈log2 k⌉)-bit borrow–save subtractor, and a w-bit carry–propagate adder. This comprises less hardware than any other reported general modulus CRT-based converter.
Efficient coverage analysis metric for HDL design validation
PLI logic for multiple-valued functions
Dynamic synchronous bandwidth allocation scheme for hard real-time communication in FDDI networks
Finite state machine encoding for VHDL synthesis
Optimisation in behavioural synthesis using hierarchical expansion: Module ripping
Weaknesses of protocols for updating the parameters of an established threshold scheme
Efficient RNS-to-binary conversion using high-radix SRT division
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