Home
>
Journals & magazines
>
IEE Proceedings - Computers and Digital Technique...
>
Volume 147
Issue 5
IEE Proceedings - Computers and Digital Techniques
Volume 147, Issue 5, September 2000
Volumes & issues:
Volume 147, Issue 5
September 2000
-
- Author(s): G. Cabodi ; P. Camurati ; C. Passerone ; S. Quer
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 147, Issue 5, p. 305 –312
- DOI: 10.1049/ip-cdt:20000684
- Type: Article
- + Show details - Hide details
-
p.
305
–312
(8)
Embedded systems are increasingly important. They are currently implemented as a mix of hardware and software components, and they must satisfy strict real-time constraints. To achieve this, several counting devices are usually introduced in the system. As a result, embedded systems exhibit extremely deep state spaces, and standard analysis methods may be excessively expensive. More specifically, there is interest in very long sequences of states without `observable' or `relevant' external effects. A new symbolic approach to represent them is described which is based on timed transition relations. The methodology may be used for a variety of applications, from synthesis to verification and to simulation. The paper concentrates on simulation. In this field, starting from a register-transfer or gate-level description, a binary-decision-diagram-based model is extracted automatically which is capable of jumping in time, avoiding the simulation of internal events. Finally, a set of experimental results obtained using a state-of-the-art simulator is discussed. - Author(s): N. Nicolici ; B.M. Al-Hashimi ; A.C. Williams
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 147, Issue 5, p. 313 –322
- DOI: 10.1049/ip-cdt:20000537
- Type: Article
- + Show details - Hide details
-
p.
313
–322
(10)
The paper describes a new technique for minimising power dissipation in full-scan sequential circuits during test application. The technique increases the correlation between successive states, during shifting in test vectors and shifting out test responses by reducing spurious transitions during test application. The reduction is achieved by freezing the primary input part of the test vector until the smallest transition count is obtained which leads to lower power dissipation. The paper presents a new algorithm which determines the primary input change time, such that maximum saving in transition count is achieved with respect to a given test vector and scan latch order. It is shown how combining the proposed technique with the recently reported scan latch and test vector ordering yields further reductions in power dissipation during test application. Exhaustive experimental results using compact and noncompact test sets demonstrate substantial savings in power dissipation using a simulated annealing-based design space exploration. As an example, saving of 34% in power dissipation for benchmark circuit s713 is achieved. - Author(s): C.D. Walter
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 147, Issue 5, p. 323 –328
- DOI: 10.1049/ip-cdt:20000638
- Type: Article
- + Show details - Hide details
-
p.
323
–328
(6)
Due to the large word lengths involved, communication and buffering are potentially the major problems in implementing the modular arithmetic used in several cryptosystems. It is shown here how a single, linear systolic array eliminates much of the associated overheads, thereby improving throughput and the ratio of speed to area for modular exponentiation. Alternative forms produce simpler processing elements and make fuller use of the hardware, making it more easily implemented in current technology. Such designs are regarded as much safer for use in smartcards and embedded systems as they offer greater protection against attacks using differential power analysis. A 1024-bit array can be built in an area comparable to a 64-bit multiplier. - Author(s): S. Jones
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 147, Issue 5, p. 329 –334
- DOI: 10.1049/ip-cdt:20000637
- Type: Article
- + Show details - Hide details
-
p.
329
–334
(6)
A novel architecture is presented for a high-performance lossless data compressor. Organised around a selectively shiftable content-addressable memory, which permits partial (inexact) matching, the processor offers very high performance with modest technology and good compression of computer-based data. Details of the operation, architecture and performance are given. - Author(s): N. Sudha ; S. Nandi ; K. Sridharan
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 147, Issue 5, p. 335 –342
- DOI: 10.1049/ip-cdt:20000635
- Type: Article
- + Show details - Hide details
-
p.
335
–342
(8)
The Euclidean distance transform (EDT) is an important tool in image analysis. Previous work on computation of EDT is limited to sequential algorithms and parallel algorithms on general purpose architectures. The authors develop a fast parallel algorithm that is amenable for VLSI implementation. The VLSI architecture is presented. Results of implementation of the VLSI design in a commercial package are also presented, and confirm the speed and suitability of the new method for real-time applications. - Author(s): J.C. Rau ; W.B. Jone ; S.C. Chang ; Y.L. Wu
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 147, Issue 5, p. 343 –348
- DOI: 10.1049/ip-cdt:20000544
- Type: Article
- + Show details - Hide details
-
p.
343
–348
(6)
A new test architecture, called TLS (tree-LFSR/SR), generates pseudo-exhaustive test patterns for both combinational and sequential VLSI circuit is presented. Instead of using a single scan chain, the proposed test architecture routes a scan tree driven by the LFSR to generate all possible input patterns for each output cone. The new test architecture is able to take advantages of both signal sharing and signal reuse. The benefits are: the difficulty of test architecture synthesis can be eased by accelerating the searching process of appropriate residues; and the number of XOR gates to satisfy the pseudo-exhaustive test criterion can be reduced. The TLS test scheme mainly contains three phases: backbone generation, tree growing, and XOR-tree generation. Experimental results obtained by simulating combinational and sequential benchmark circuits are very encouraging. - Author(s): R. Drechsler ; B. Becker ; N. Drechsler
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 147, Issue 5, p. 349 –353
- DOI: 10.1049/ip-cdt:20000743
- Type: Article
- + Show details - Hide details
-
p.
349
–353
(5)
A genetic algorithm (GA) is developed to find small or minimal fixed polarity Reed-Muller expressions (FPRMs) for large functions. The authors combine the GA with greedy heuristics, i.e. They use hybrid GAs (HGAs). They show by experiments that results superior to all other approaches for large functions can be obtained using GAs. This mainly results from the use of a problem specific data structure and the incorporation of heuristics in the GA. - Author(s): A. Sesmun and L.F. Turner
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 147, Issue 5, p. 355 –363
- DOI: 10.1049/ip-cdt:20000741
- Type: Article
- + Show details - Hide details
-
p.
355
–363
(9)
Conventional network design techniques treat the concepts of performance and reliability separately. This approach ensures that reliability requirements are met and performance specifications are satisfied when all components are operational. However, it does not guarantee a graceful degradation of the performance of the network under conditions of failure. In order to derive a fault-tolerant network, it is necessary to design the network with respect to a combined measure of performance and reliability. Such a measure originated in the early 1980s and is referred to as performability. The authors propose a technique that uses performability in the design of communication networks, with the objective of deriving a design methodology for fault-tolerant networks. The benefits of using this approach, compared with conventional design methods, are illustrated by means of a design example. - Author(s): W.-H. He and T.-C. Wu
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 147, Issue 5, p. 365 –368
- DOI: 10.1049/ip-cdt:20000744
- Type: Article
- + Show details - Hide details
-
p.
365
–368
(4)
The authors show that two proposed password-based user authentication and access control schemes by Jan and Tseng are not secure against impersonation attack, i.e. an adversary can successfully pretend to be any legitimate user and take over all access rights granted to that user without being detected. The authors also present corrections to these two schemes, and provide the same administration functions as orignally intended.
Exploiting timed transition relations in sequential cycle-based simulation of embedded systems
Minimisation of power dissipation during test application in full-scan sequential circuits using primary input freezing
Improved linear systolic array for fast modular exponentiation
Partial-matching lossless data compression hardware
Cellular architecture for Euclidean distance transformation
Tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits
Genetic algorithm for minimisation of fixed polarity Reed-Muller expressions
Using performability in the design of communication networks
Security of the Jan-Tseng integrated schemes for user authentication and access control
Most viewed content for this Journal
Article
content/journals/ip-cdt
Journal
5
Most cited content for this Journal
We currently have no most cited data available for this content.