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Volume 147
Issue 2
IEE Proceedings - Computers and Digital Techniques
Volume 147, Issue 2, March 2000
Volumes & issues:
Volume 147, Issue 2
March 2000
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- Author(s): A. Z̆emva ; A. Trost ; B. Zajc
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 147, Issue 2, p. 53 –58
- DOI: 10.1049/ip-cdt:20000275
- Type: Article
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53
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The concept of permissible logic perturbations is introduced as a method for logic optimisation of multi-level digital circuits. The presented approach, denoted as a wave synthesis, refers to a sequence of procedures performed in order of logic levels that transform a perturbation region of multi-input, multi-output wires into a multi-input, multi-output logic subcircuit. The primary goal of the wave synthesis, which in contrast to the other methods for logic optimisation relies on fault simulation and test pattern generation algorithms, is the area optimisation of the initial technology-independent multi-level circuit. The wave synthesis concept is verified for several multi-input, multi-output combinational circuits and experimental results confirm the feasibility of the presented approach. - Author(s): N. Mani and N.H. Quach
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 147, Issue 2, p. 59 –64
- DOI: 10.1049/ip-cdt:20000260
- Type: Article
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59
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New heuristics in solving the maze routing problem are presented. The proposed MQ algorithm generates a shortest path based on the depth-first vertex traversal approach in the direction towards the target. A set of heuristics is formulated by assigning a directional priority sequence to each vertex while finding the path. This method will find a shortest path between two points, if one exists, on a rectangular grid-of vertices. Some vertices, named blocking vertices, are occupied by other circuitry or by paths already routed, and hence are not available for routing. Blocking vertices are introduced as a means of modelling obstacles during the path finding process. An implementation of the algorithm and its experimental results are also reported. - Author(s): C.-C. Wang ; P.-M. Lee ; C.-J. Huang
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 147, Issue 2, p. 65 –74
- DOI: 10.1049/ip-cdt:20000382
- Type: Article
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65
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Inner-product calculations are often required in digital neural computing. The critical path of the inner product of two binary vectors is the carry propagation delay generated from individual product terms. Three alternative architecture for arranging digital ratioed compressors are presented, to reduce the carry propagation delay in the critical path wherein an improved design of a 3-2 compressor is used to serve as the basic building element. The carry propagation delay estimation for the there architectures is also derived and compared. The theoretical analyses and Verilog simulations both indicate that one of the architectures presented might offer a sub-optimal solution for summing the individual product terms in the inner-product computation. Furthermore, a real chip for the sub-optimal architecture was fabricated and fully tested. The testing results prove the correctness of its functions and performance. - Author(s): C.W. Chen ; N.P. Lu ; T.F. Chen ; C.P. Chung
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 147, Issue 2, p. 75 –81
- DOI: 10.1049/ip-cdt:20000185
- Type: Article
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75
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The authors propose two single-fault-tolerant gamma interconnection networks. The first is a partially chained gamma interconnection network (PCGIN) with two disjoint paths between any source-destination pair. A PCGIN has the characteristics of one fault tolerance and destination tag routing, but backtracking may be necessary when a fault occurs. To eliminate the backtracking penalties of a PCGIN, a fully chained gamma interconnection network (FCGIN); that can at least tolerate one link or switch fault at each stage without backtracking, is also proposed FCGIN has the advantages of destination tag routing, lower hardware costs than a PCGIN, low fault penalty, and strong reroutability. - Author(s): P.-A. Hsiung
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 147, Issue 2, p. 83 –92
- DOI: 10.1049/ip-cdt:20000452
- Type: Article
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83
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The results of hardware-software codesign of concurrent embedded real-time systems are often not verified or not easily verifiable. This has serious consequences when high-assurance systems are codesigned. The main difficulty lies in the different time-scales of the embedded hardware, of the embedded software, and of the environment. This difference makes hardware-software timing coverification not only a difficult task for most systems, but has also restricted coverification to the initial system specifications. Currently, most codesign tools or methodologies only support validation in the form of cosimulation and testing of design alternatives. Here, a new formal coverification approach is proposed based on linear hybrid automata. The basic timing problems found in most coverification tasks are presented and solved. For complex systems, a simplification strategy is proposed to attack the state-space explosion occurring in formal coverification. Experimental results show the feasibility of the approach and the increase in verification scalability through the application of the proposed method. - Author(s): A. De Gloria and M. Olivieri
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 147, Issue 2, p. 93 –100
- DOI: 10.1049/ip-cdt:20000451
- Type: Article
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93
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Logic analysis, circuit implementation and verification of a novel self-timed adder scheme based on carry select (CS) logic are presented. The preliminary analysis of the variable-time behaviour of CS logic justifies the design of self-timed CS adders, and identifies the best choice for the block size to optimise the average performance. The logic design and full-custom circuit implementation is described of a completion-detecting CS adder by means of precharged CMOS logic. The correct asynchronous operation of the circuit is verified by means of layout level SPICE simulation referring to a 0.35 μm CMOS process. The worst-case addition time is comparable with the fastest fixed-time adders, which is a considerable result for a completion-detecting technique. The hardware overhead can be limited to 23% over a conventional CS adder. SPICE simulation estimates an average detected addition time of 1.6 ns for a 64 bit adder, including the precharge time. - Author(s): R.-M. Shiu ; J.-C. Chiu ; S.-K. Cheng ; J.J.-J. Shann
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 147, Issue 2, p. 101 –107
- DOI: 10.1049/ip-cdt:20000450
- Type: Article
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p.
101
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The paper examines the design issues of decoders, including the primitive operation (POP) translation strategies and the decoding rules, for CISC superscalar processors to exploit a higher degree of parallel execution. Attention is focused on the x86 instruction set because of its popularity. There are two different approaches regarding POP translation strategies: one is to merge the address generation into load/store operations, and the other is to translate the isolated address generation operations. Simulation results show that, in high issue-rate decoders, the latter strategy improves the performance by 20 to 25%. Furthermore, considering the tradeoffs between the hardware cost and performance, a cost-effective decoding rule suitable for current commercial programs is recommended. - Author(s): C.-C. Wang ; C.-J. Huang ; G.-C. Lin
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 147, Issue 2, p. 109 –115
- DOI: 10.1049/ip-cdt:20000160
- Type: Article
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p.
109
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A high-speed 64b/32b integer divider using the digit-recurrence division method and the on-the-fly conversion algorithm, is presented. A fast normaliser is used as the preprocessor of the proposed integer divider. To reduce maximum division time, the proposed divider uses radix-4/2 division, instead of the traditional radix-2 division. On-the-fly quotient adjustment is also realised in the converter module of the divider. The entire design is written in the Verilog hardware description language using the COMPASS 0.6 μm 1P3M cell library (V3.0), and then synthesised by SYNOPSYS. Finally a real chip is fabricated and fully tested. The test results are very impressive. A performance evaluation of a 128b/64b signed integer divider using the same design methodology is also included in this study. - Author(s): S.-M. Moon and S. Park
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 147, Issue 2, p. 117 –123
- DOI: 10.1049/ip-cdt:20000186
- Type: Article
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117
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VLIW machines derive their performance advantage from the parallel execution of independent instructions that have been scheduled by the compiler. The paper evaluates the performance impact of a set of important VLIW compilation techniques on non-numerical integer programs. In particular, several key scheduling approaches, including software pipelining versus loop unrolling, DAG-based versus trace-based global scheduling, all-path versus profiled speculation, and restricted versus unrestricted speculative loads, are compared. The evaluation is performed on a uniform VLIW testbed where a relatively fair comparison of these scheduling approaches can be made. The result provides a meaningful insight into the relative benefits of each approach. - Author(s): J. Yoon and H. Kim
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 147, Issue 2, p. 125 –132
- DOI: 10.1049/ip-cdt:20000190
- Type: Article
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p.
125
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A time-redundant approach is proposed by adopting a rollback and/or roll-forward technique to recover TMR failures producing incorrect majority outputs in a TMR (structured) system that uses the simplest spatial redundancy. This technique is apparently effective in recovering TMR failures primarily caused by transient faults. The proposed policies carry out fewer reconfigurations at the cost of (minimal) time overhead needed for applying those time-redundant schemes. Specifically, two methods are presented (flexibly used) for the recovery policy to guarantee high reliability. The optimal checkpoint vectors are also derived for both methods by using the likelihoods of all possible failure states as well as the total execution time. Consequently, the effectiveness of the proposed policy is validated through certain numerical examples and computer simulation.
Multi-level logic optimisation based on permissible perturbations
Heuristics in the routing algorithm for circuit layout design
Three alternative architectures of digital ratioed compressor design with application to inner-product processing
Fault-tolerant gamma interconnection networks by chaining
Hardware-software timing coverification of concurrent embedded real-time systems
Completion-detecting carry select addition
Decoding of CISC instructions in superscalar processors with high issue rate
Cell-based implementation of radix-4/2 64b dividend 32b divisor signed integer divider using the COMPASS cell library
Performance analysis of VLIW compilation techniques
Time-redundant recovery policy of TMR failures using rollback and roll-forward methods
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