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Volume 146
Issue 4
IEE Proceedings - Computers and Digital Techniques
Volume 146, Issue 4, July 1999
Volumes & issues:
Volume 146, Issue 4
July 1999
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- Author(s): L. Benini ; G. De Micheli ; A. Macii ; E. Macii ; M. Poncino
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 146, Issue 4, p. 173 –178
- DOI: 10.1049/ip-cdt:19990419
- Type: Article
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p.
173
–178
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A methodology is presented for automatically determining an assignment of instruction op-codes that guarantees the minimisation of bit transitions occurring inside the registers of the pipeline stages involved in instruction fetching and decoding. The assignment of the binary patterns to the op-codes is driven by the statistics concerning instruction adjacency collected through instruction-level simulation of typical software applications. Therefore the technique is best exploited when applied to encode the instruction set of core processors and microcontrollers, since components of these types are commonly used to execute fixed portions of machine code within embedded systems. The effectiveness of the methodology is illustrated through experimental data obtained on a realistic case study, namely, the MIPS R4000 RISC microprocessor. - Author(s): P. -J. Chuang and H. -Y. Tu
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 146, Issue 4, p. 179 –184
- DOI: 10.1049/ip-cdt:19990421
- Type: Article
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p.
179
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The presence of hot spots in a Multistage interconnection network (MIN) can impair message transmission, increasing average delay time and jeopardising system performance. To reduce the hot-spot impact in the cyclic gamma interconnection network, a MIN design with multiple disjoint paths between every communication pair, a static routing scheme is presented to trim down average system delay time when the majority of message patterns is asynchronous. To further reduce average system delay time regardless of transmission patterns, a dynamic routing and rerouting scheme is proposed. Extensive simulation has been conducted to evaluate the performance of the proposed schemes and some other schemes. Results show that the proposed dynamic scheme can reduce the hot-spot impact more effectively at no extra cost. - Author(s): S. R. Blackburn
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 146, Issue 4, p. 185 –186
- DOI: 10.1049/ip-cdt:19990526
- Type: Article
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p.
185
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The paper cryptanalyses the Wu-Dawson public key cryptosystem. - Author(s): T. H. Han and S. H. Hwang
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 146, Issue 4, p. 188 –195
- DOI: 10.1049/ip-cdt:19990592
- Type: Article
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188
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A novel architecture for the block matching technique is proposed, which can flexibly deal with various sizes of matching block and miscellaneous motion vector prediction modes of the current video coding standards, without extra area and control overhead. The processing element array of the proposed architecture features a separate difference and accumulation unit, considering the balanced delay time among operational data paths and efficient hardware resource utilisation. The VLSI realisation of the proposed architecture using 0.6μm CMOS technology shows significant improvement over a conventional systolic architecture in both area and speed. - Author(s): L. Wang ; A. E. A. Almaini ; A. Bystrov
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 146, Issue 4, p. 197 –204
- DOI: 10.1049/ip-cdt:19990525
- Type: Article
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p.
197
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The concept of polarity for canonical sum-of-products (SOP) Boolean functions is introduced. This facilitates efficient conversion between SOP and fixed polarity Reed-Muller (FPRM) forms. New algorithms are presented for the bidirectional conversion between the two paradigms. Multiple segment and multiple pointer techniques are employed to achieve fast conversion for large Boolean functions. Experimental results are given using a personal computer with Cyrix 6x86-166 CPU and 32MB RAM. The results show that the algorithm is very efficient in terms of time and space for large Boolean functions. - Author(s): C. -L. Wey and C. -P. Wang
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 146, Issue 4, p. 205 –210
- DOI: 10.1049/ip-cdt:19990524
- Type: Article
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p.
205
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The design of a fast divider is an important issue in high-speed computing. The paper presents a fast radix-4 SRT division architecture. Instead of finding the correct quotient digit, an estimated quotient digit is first speculated. The speculated quotient digit is used to simultaneously compute the two possible partial remainders for the next step while the quotient digit is being corrected. Thus, this two-step process does not influence the overall speed. Since the decision-making circuits can be implemented with simple gate structures, the proposed divider offers fast speed operation. Based on the physical layout, the circuit takes 247ns for a double precision division (56 bits for fraction part), where the 2μm CMOS technology in MAGIC is employed and simulated. - Author(s): B. Sallay ; P. Maestrini ; P. Santi
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 146, Issue 4, p. 211 –215
- DOI: 10.1049/ip-cdt:19990438
- Type: Article
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p.
211
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A promising application of comparison-based system-level diagnosis is the testing of VLSI chips during manufacture. However, existing comparison models essentially overlook the test invalidation owing to the physical faults in the comparators. A comparison model is proposed that takes into account faults affecting the comparators and the syndrome generation circuitry. A comparator test session is described that is capable of detecting any combination of stuck-at faults in the diagnostic-circuitry. This test requires units on the wafer to use independent test inputs which can be satisfied at a small wafer design cost. - Author(s): K. J. Tan ; S. J. Gu ; H. W. Zhu
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 146, Issue 4, p. 217 –218
- DOI: 10.1049/ip-cdt:19990422
- Type: Article
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p.
217
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Two counter-examples point out that a CHW cryptographic key assignment scheme in a hierarchy and its two modified versions are impractical or incorrect. - Author(s): M. -S. Hwang
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 146, Issue 4, page: 219 –219
- DOI: 10.1049/ip-cdt:19990552
- Type: Article
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p.
219
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An extension of the CHW cryptographic key assignment scheme in a hierarchy can defend against attacks using Tan, Gu and Zhus' methods.
Automatic selection of instruction op-codes of low-power core processors
Dynamic scheme for reducing hot-spot effects in multipath networks
Cryptanalysis of a public key cryptosystem proposed by Wu and Dawson
Versatile architecture for block matching motion estimation
Efficient polarity conversion for large Boolean functions
Design of a fast radix-4 SRT divider and its VLSI implementation
Wafer-scale diagnosis tolerating comparator faults
Correctness of CHW cryptographic key assignment scheme in a hierarchy
Extension of CHW cryptographic key assignment scheme in a hierarchy
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