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Volume 145
Issue 4
IEE Proceedings - Computers and Digital Techniques
Volume 145, Issue 4, July 1998
Volumes & issues:
Volume 145, Issue 4
July 1998
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- Author(s): S. Park and G. Lee
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 4, p. 249 –254
- DOI: 10.1049/ip-cdt:19982023
- Type: Article
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p.
249
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(6)
To overcome the large hardware overhead attendant in the full scan design, the concept of partial scan design has emerged with the virtue of less area and testability close to full scan. A ‘combinational structure’ has been developed to avoid the use of a sequential test generator. But test patterns shifted on the scan register have to be held for a sequential depth period upon the aid of the dedicated HOLD circuit. In this paper a new levellised structure is introduced aiming to exclude the need for an extra HOLD circuit. The time to stimulate each scan latch is uniquely determined on this structure, hence each test pattern can be applied by scan shifting and then pulsing a system clock like the full scan, but with many fewer scan flip-flops. Experimental results show that some sequential circuits are levellised by just scanning self-loop flip-flops. - Author(s): N.-P. Lu and C.-P. Chung
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 4, p. 255 –264
- DOI: 10.1049/ip-cdt:19981955
- Type: Article
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p.
255
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(10)
To exploit more parallelism in programs, superscalar multiprocessor systems, which exploit both fine-grained and coarse-grained parallelism, have been the trend in designing high-speed computing systems. Recently, the authors have developed a simulator for evaluating superscalar multiprocessor systems. This simulator models both a superscalar processor that can exploit instruction-level parallelism, and a shared-memory multiprocessor system that can exploit task-level parallelism. This simulator was used to run four applications chosen from the SPLASH-2 benchmark suite, and collected some performance data to investigate the parallelism exploitation capability of the superscalar multiprocessor systems in various configurations. It was observed that the instruction-level and task-level parallelism in programs can be exploited well by a moderate degree of superscalar processing and a high degree of multiprocessing. For example, the speedup of a 32-way multiprocessor with eight-issue processors can be over 200 relative to a single-issue uniprocessor. - Author(s): Ç.K. Koç and C.Y. Hung
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 4, p. 265 –271
- DOI: 10.1049/ip-cdt:19982091
- Type: Article
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p.
265
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The paper presents an algorithm for computing the residue R = X mod M. The algorithm is based on a sign estimation technique that estimates the sign of a number represented by a carry-sum pair produced by a carry save adder. Given the (n + k)-bit X and the n-bit M, the modular reduction algorithm computes the n-bit residue R in O(k + log n) time, and is particularly useful when the operand size is large. We also present a variant of the algorithm that performs modular multiplication by interleaving the shift-and-add and the modular reduction steps. The modular multiplication algorithm can be used to obtain efficient VLSI implementations of exponentiation cryptosystems. - Author(s): J.-H. Guo and C.-L. Wang
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 4, p. 272 –278
- DOI: 10.1049/ip-cdt:19982092
- Type: Article
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p.
272
–278
(7)
Two parallel-in parallel-out systolic arrays for computing inverses and divisions in finite fields GF(2m) with the standard basis representation are presented. Both architectures realise a new variant of Euclid's algorithm. One of the proposed arrays involves O(m2) area complexity and O(1) time complexity, while the other involves O(m) area complexity and O(m) time complexity. They are highly regular, modular and thus well suited to VLSI implementation. Compared to existing related systolic architectures with the same time complexity, our proposed arrays involve less chip area and smaller latency. It should be noted that, to perform inversion only, both the proposed arrays can be simplified. - Author(s): C.-C. Wang ; C.-F. Tsai ; J.-P. Lee
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 4, p. 279 –285
- DOI: 10.1049/ip-cdt:19982017
- Type: Article
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p.
279
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The exponential bidirectional associative memory (eBAM) is a high-capacity associative memory. However, in the hardware realisation of eBAM, increasing efforts have been made to obtain an optimally small radix of exponential circuit for the fixed dynamic range of the VLSI circuit transistor, thereby allowing the dimension of the stored patterns to reach maximum. In this paper, the authors prove the stability of eBAM. The absolute lower bound of the radix of the eBAM is also obtained. In addition, an algorithm is presented to compute the optimal radix of an exponential circuit. To preserve the optimality of the radix, an algorithm capable of updating the radix when new pattern pairs are to be installed is proposed. Moreover, a deterministic method is presented to train and install pattern pairs with a predetermined fault tolerance ability. - Author(s): M.-H. Yang ; J.-W. Lee ; S. Kang
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 4, p. 287 –291
- DOI: 10.1049/ip-cdt:19982093
- Type: Article
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p.
287
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The main objective of this paper is to develop an efficient algorithm and architecture for scan conversion in high definition television. Scan conversion requires rapid operations of a large amount of image signal data, thus complex algorithm, architecture, and a large memory are necessary. A simple and effective interpolation method and a pipelined parallel architecture using memory partitioning for the real time operation are proposed. In the new interpolation algorithm, the new image data with edge direction information can be obtained using a simple calculation which considers six neighbouring pixels. To reduce the operation time and memory size, a pipelined parallel architecture is used, and the memory is partitioned into several memory banks. Thus, only small operations with a small memory and short operation time, are needed for the new algorithm and architecture. - Author(s): W. Jia and W. Zhao
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 4, p. 292 –300
- DOI: 10.1049/ip-cdt:19982094
- Type: Article
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p.
292
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A novel reliable, totally ordered multicast protocol on a single logical process ring (called FTSM) is presented. It guarantees totally ordered and atomic delivery of multicast messages in the presence of message loss, site crashes and network partitioning. By placing sequence numbers on messages, a process holding a virtual token multicasts totally ordered messages. Atomic delivery of multicast messages is achieved by piggybacking stable and acknowledged information on the part of both sender and receivers. Virtual token passing and transmission of control messages are piggybacked onto ordered data messages without requiring additional communication overhead. Individual processes handle token passing and control information by applying a local heuristic. FTSM is scaleable because its overhead on achieving total ordering and atomicity does not depend on the size of the process group. Implementation demonstrates that FTSM achieves superior performance over existing protocols in the same hardware setting. - Author(s): J.–Y. Jou and D.–S. Chou
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 4, p. 301 –307
- DOI: 10.1049/ip-cdt:19982018
- Type: Article
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p.
301
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Because the average power consumption of CMOS digital circuits is proportional to the square of the supplied voltage, a clustered voltage scaling (CVS) technique has previously been proposed to reduce power without sacrificing the circuit performance. In this paper the authors propose a path-oriented CVS algorithm, which can take the false paths into account. Extensive experiments are conducted on ISCAS85 benchmark circuits. These experiments show that many more gates can be voltage scaled down in comparison with the original CVS technique. An additional 22% power reduction ratio over that of the original CVS technique is achieved. - Author(s): C. Gil and J. Ortega
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 4, p. 308 –316
- DOI: 10.1049/ip-cdt:19982024
- Type: Article
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p.
308
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In the last few years new test generation procedures based on Boolean techniques have been reported. Despite the fact that Boolean operations are in general computationally expensive and that procedures are available based on path-oriented methods of reasonable efficiency, there is still interest in developing new methods to speed up the detection of those faults that are hard to detect by the path-oriented methods, to reduce the test lengths obtained, or to make it possible to use parallel machines more efficiently. A new algebraic procedure to determine test patterns for stuck-line faults in combinational logic circuits is proposed. It is based on the use of Reed–Muller coefficients to build and solve the equation that describes the Boolean difference between the circuit affected by a given fault and the correct one. It is also shown how digital spectral techniques, which have been widely used in the synthesis of switching functions and in the determination of circuit signatures for built-in self testing, can also be applied to the test-pattern generation problem. The procedure has proved its efficiency when applied to the standard ISCAS benchmark circuits. - Author(s): J.–H. Oh and S.–J. Moon
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 4, p. 317 –318
- DOI: 10.1049/ip-cdt:19982095
- Type: Article
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p.
317
–318
(2)
The Montgomery algorithm has been widely used in modern cryptography because it is effective for modular exponentiation. However, it is not efficient when used for just a few modular multiplications. Inefficiency is due to the large overhead involved in the residue transformation of arguments. A new modular multiplication method using the Montgomery reduction algorithm is presented which can eliminate the demerit of the Montgomery algorithm in the case of just a few modular multiplications. - Author(s): J.–T. Yan
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 4, p. 319 –320
- DOI: 10.1049/ip-cdt:19982096
- Type: Article
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p.
319
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A new routing model with constrained terminal structure for over-the-cell channel routing and a graph theoretical algorithm for solving the planar constrained terminals over-the-cell routing problem have recently been published. The routing model with constrained terminal structure assigns the connection constraint between adjacent layers on terminals and makes use of the vacant locations on each layer for over-the-cell routing. Based on the constrained terminal structure, a graph theoretical algorithm is proposed to complete planer routing layer by layer for over-the-cell channel routing. The new routing model and the graph theoretical algorithm are shown to be flawed, and corrections are suggested.
Partial scan design based on levellised combinational structure
Parallelism exploitation in superscalar multiprocessing
Fast algorithm for modular reduction
Hardware-efficient systolic architecture for inversion and division in GF(2m)
Analysis of radix searching of exponential bidirectional associative memory
Efficient algorithm and architecture for scan conversion in HDTV
Fault-tolerant scaleable multicast algorithm with piggybacking approach on logical process ring
Sensitisable-path-oriented clustered voltage scaling technique for low power
Algebraic test-pattern generation based on the Reed–Muller spectrum
Modular multiplication method
Correspondence on ‘Planar constrained terminals over-the-cell router’
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