Home
>
Journals & magazines
>
IEE Proceedings - Computers and Digital Technique...
>
Volume 145
Issue 3
IEE Proceedings - Computers and Digital Techniques
Volume 145, Issue 3, May 1998
Volumes & issues:
Volume 145, Issue 3
May 1998
-
- Author(s): J. Harrison
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 3, page: 153 –153
- DOI: 10.1049/ip-cdt:19982052
- Type: Article
- + Show details - Hide details
-
p.
153
(1)
- Author(s): M. Benmohammed and A. Rahmoune
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 3, p. 155 –160
- DOI: 10.1049/ip-cdt:19981970
- Type: Article
- + Show details - Hide details
-
p.
155
–160
(6)
Existing techniques in high-level synthesis mostly assume a simple controller model in the form of a single FSM. In reality more complex controller architectures are often used. On the other hand, in the case of programmable processors the controller architecture is largely defined by the available control-flow instructions in the instruction set. With the wider acceptance of behavioural synthesis, the application of these methods for the design of programmable controllers is of fundamental importance in embedded system technology. An important extension of an existing architectural synthesis system targeting the generation of reprogrammable microcoded controllers is described. The designer can then generate both styles of architecture, hardwired and programmable, using the same synthesis system and can quickly evaluate the trade-offs of hardware decisions. - Author(s): M. Deegener and S.A. Huss
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 3, p. 161 –170
- DOI: 10.1049/ip-cdt:19981969
- Type: Article
- + Show details - Hide details
-
p.
161
–170
(10)
Embedded systems, which combine an implementation of their functionality in hardware and software, are of increasing interest to information processing in dedicated systems of various areas, such as automotive, instrumentation, robotics or telecom. The requirements of such systems impose a new design methodology known as codesign, and result in co-operating engineering efforts to conceive and to implement efficiently the functionality of an embedded system. This paper presents an approach to an exploration and assessment of feasible solutions from a large design space. The conceptual design phase of embedded systems is emphasised, resulting in efficient methods to capture design specifications, to generate feasible solutions from basic design decisions, and to validate these solutions. The proposed methods are demonstrated for an embedded system for telecom applications. - Author(s): R. Esser ; J. Teich ; L. Thiele
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 3, p. 171 –180
- DOI: 10.1049/ip-cdt:19981973
- Type: Article
- + Show details - Hide details
-
p.
171
–180
(10)
A modelling environment is described for the automated design of embedded systems. The basic model of computation consists of a class of high-level time Petri nets augmented with object-oriented mechanisms. It is formal, ensuring unambiguous specification, supports a high level of analysis and is general enough to support other more specialised formalisms. This model constitutes a major part of the CodeSign design methodology developed at the ETH, Zürich - Author(s): G.F. Marchioro ; J.M. Daveau ; T.B. Ismail ; A.A. Jerraya
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 3, p. 181 –196
- DOI: 10.1049/ip-cdt:19981971
- Type: Article
- + Show details - Hide details
-
p.
181
–196
(16)
This paper presents the underlying methodology of Cosmos, an interactive approach for hardware/software codesign capable of handling multiprocessor systems and distributed architectures. The approach covers the codesign process through a set of user guided transformations allowing semiautomatic partitioning. The transformations are based on a powerful set of primitives for functional partitioning, structural reorganisation and communication transformation. It leads to a fast transformation of a system-level specification into an architecture with a short design time and easy exploration of design space. The application of this approach is illustrated using two design examples starting from a system-level specification given in SDL to a distributed hardware/software architecture described in C/VHDL. We show that the use of transformational approach allows: (i) application of the expertise of the designer during partitioning; (ii) the user to understand the results of the codesign process; (iii) the process to take into account partial existing solutions; (iv) easy design space exploration; (v) the designer to start from a very high-level specification language of the system to be designed. - Author(s): J. Hou and W. Wolf
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 3, p. 197 –202
- DOI: 10.1049/ip-cdt:19981974
- Type: Article
- + Show details - Hide details
-
p.
197
–202
(6)
A novel presynthesis algorithm for partitioning processes in distributed embedded computing systems is presented. The approach redesigns the task graph specification for a system to partition the processes that comprise the tasks into efficiently sized units of computation. Partitioning estimates the total system performance by estimating the final allocation of processes to processing elements. The algorithm tries to reduce process overhead while maintaining the parallelism necessary to achieve the required system performance. Experimental results show that the presynthesis technique can significantly improve both the CPU time and results obtained from cosynthesis. - Author(s): X. Hu and G. Greenwood
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 3, p. 203 –209
- DOI: 10.1049/ip-cdt:19981972
- Type: Article
- + Show details - Hide details
-
p.
203
–209
(7)
The authors present an approach to hardware/software codesign of real-time embedded systems. Two of the difficulties associated with codesign are handling tradeoffs among multiple attributes and exploring a large design space. They use a combination of techniques from the evolutionary computation and utility theory fields to address these problem areas. A real-time microcontroller-based design example is presented to illustrate this approach.
Editorial: Hardware/software codesign for embedded systems
Automatic generation of reprogrammable microcoded controllers within a high-level synthesis environment
Design space exploration techniques for the codesign of embedded data processing systems
CodeSign: An embedded system design environment
Transformational partitioning for codesign
Presynthesis partitioning for hardware/software cosynthesis
Evolutionary approach to hardware/software partitioning
-
- Author(s): R.S. Tan and V. Lakshmi Narasimhan
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 3, p. 211 –214
- DOI: 10.1049/ip-cdt:19981936
- Type: Article
- + Show details - Hide details
-
p.
211
–214
(4)
LSOM (load-balancing self-organising map), a neural network based on Kohonen's self-organising map, is proposed for the problem of mapping finite element method (FEM) grids to distributed memory parallel computers with mesh interconnection networks. The rough global ordering produced by LSOM is combined with the local refinement Kernighan–Lin algorithm (LSOM-KL) to obtain the solution. LSOM-KL achieved a load imbalance of less than 0.1% and a low number of hops, comparable to results obtained with commonly used recursive bisection methods. - Author(s): S.-M. Moon ; H.M. Chung ; J. Park ; S.M. Shim ; J.-W. Ahn
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 3, p. 215 –224
- DOI: 10.1049/ip-cdt:19982025
- Type: Article
- + Show details - Hide details
-
p.
215
–224
(10)
The performance of very long instruction word (VLIW) microprocessors depends on the close co-operation between the compiler and the architecture. To design a high-performance VLIW a testbed is required that allows detailed co-evaluation of both compilation techniques and architectural features. The paper introduces a new VLIW testbed based on the SPARC instruction set architecture, which includes an aggressive scheduling compiler and a fast VLIW simulator. The compiler takes gcc-generated optimised SPARC code as input and generates parallelised VLIW code, targeting advanced VLIW architectures. The compiler can generate high-performance VLIW code, especially for non-numerical integer programs. The VLIW code is translated into a dedicated C program for fast and simple compiled simulation which generates detailed data for performance evaluation. The authors have performed a comprehensive empirical study on the testbed for both large-resource and small-resource machines. The result shows that a geometric mean of as much as fourfold speedup is obtainable on nontrivial integer benchmarks without using branch probability when performing speculative code motion. Also analysed are the characteristics of the useful and useless ALU operations in each cycle to see how the speedup is obtained. The analysis indicates that around half of the useful ALUs execute speculative instructions whose original paths are taken (thus being ‘hit’), yet a substantial number of ALUs are also wasted owing to useless speculative execution or copy execution. - Author(s): H. Nassar and J.D. Carpinelli
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 3, p. 225 –228
- DOI: 10.1049/ip-cdt:19981939
- Type: Article
- + Show details - Hide details
-
p.
225
–228
(4)
Interconnection networks are central components in two different environments: multiprocessor systems and ATM switching systems. They have been analysed extensively in either one of the two environments. However, most of the analyses assume uniform traffic. Only recently have some analyses considered nonuniform traffic, but with some restrictions either on the traffic or on the network. In this paper the authors remove these restrictions, and analyse an arbitrary network under arbitrary nonuniform traffic. The authors have validated the models with Monte Carlo simulation. - Author(s): T. Srikanthan ; M. Bhardwaj ; C.T. Clarke
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 3, p. 229 –235
- DOI: 10.1049/ip-cdt:19981948
- Type: Article
- + Show details - Hide details
-
p.
229
–235
(7)
The authors present highly area–time-efficient VLSI implementations of residue reverse converters called compressed multiply accumulate (CMAC) converters. This efficiency results from carefully identifying and eliminating redundancy in existing proposals. Specifically, the partial sum generation and addition are merged into a single carry-save addition operation. Also, modulo multipliers are replaced by simple adders by the bit unfolding and uncorrected residues technique. The CMAC reverse converters proposed here were fabricated in a 0.8 µm N-well CMOS process. Due to the techniques mentioned, the resulting VLSI implementation was 3–4 times smaller than recently reported results, while delivering identical throughput and achieving four times lower delay. The AT2 efficiency of these converters O(n2log3n) equals the best known to date. Comprehensive analysis of the various implementation options (CPA, CLA or serial) presented will be of great value to the VLSI system designer in choosing a reverse converter that conforms to the delay, area and power requirements imposed by a given application. - Author(s): J.J. Woźniak
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 3, p. 237 –241
- DOI: 10.1049/ip-cdt:19981938
- Type: Article
- + Show details - Hide details
-
p.
237
–241
(5)
The paper presents a systolic serial dual basis multiplier for the Galois field GF(2m) which is based on the Berlekamp-like multiplication algorithm. It needs only one control signal and is easy to simplify for the field which is generated by the irreducible polynomial xm + x + 1. The multiplier's architecture is highly regular, modular and easily expandable, hence it is suitable for implementation using VLSI technologies. - Author(s): C. Ortega-Sanchez and A. Tyrrell
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 145, Issue 3, p. 242 –248
- DOI: 10.1049/ip-cdt:19981940
- Type: Article
- + Show details - Hide details
-
p.
242
–248
(7)
Embryonic systems are cellular arrays with reconfiguration characteristics similar to those found in biological cellular organisms. Properties such as multicellular organisation, cellular differentiation and cellular division provide embryonic arrays with biological-like fault tolerance properties. This paper presents the detailed description of a basic cell to be used as the building block of embryonic arrays. The implementation and simulation of a voter circuit and a counter are presented as examples to show the effectiveness of embryonic arrays in terms of functionality and fault-tolerance.
Mapping finite element grids onto parallel multicomputers using a self-organising map
SPARC-based VLIW testbed
Generalised model for Banyan networks with nonuniform traffic
Area-time-efficient VLSI residue-to-binary converters
Systolic dual basis serial multiplier
Design of a basic cell to construct embryonic arrays
Most viewed content for this Journal
Article
content/journals/ip-cdt
Journal
5
Most cited content for this Journal
We currently have no most cited data available for this content.
