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Volume 144
Issue 1
IEE Proceedings - Computers and Digital Techniques
Volume 144, Issue 1, January 1997
Volumes & issues:
Volume 144, Issue 1
January 1997
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- Author(s): T.P.K. Nijhar and A.D. Brown
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 144, Issue 1, p. 1 –6
- DOI: 10.1049/ip-cdt:19970631
- Type: Article
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Optimisation in high level behavioural synthesis is usually performed by applying transforms to the datapath and control graphs. An alternative approach, however, is to apply transforms at a higher level in the process, specifically directly to the behavioural source description. This technique is analogous to the way in which the source code of a conventional sequential programming language may be processed by an optimising compiler. The application of this kind of preprocessing to a number of example behavioural VHDL source descriptions (which are then fed into a ‘conventional’ synthesis system) produces structural descriptions which are up to 32% smaller and 52% faster. - Author(s): A. Symons and V. Lakshmi Narasimhan
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 144, Issue 1, p. 7 –14
- DOI: 10.1049/ip-cdt:19970961
- Type: Article
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Currently many interconnection networks and parallel algorithms exist for message-passing computers. Users of these machines wish to determine which message-passing computer is best for a given job, and how it will scale with the number of processors and algorithm size. The paper describes a general purpose simulator for message-passing multiprocessors (Parsim), which facilitates system modelling. A structured method for simulator design has been used which gives Parsim the ability to simulate different topologies and algorithm combinations easily. This is illustrated by applying Parsim to a number of algorithms on a variety of topologies. Parsim is then used to predict the performance of the new IBM SP2 parallel computer, with topologies ranging up to 1024 processors. - Author(s): C.N. Zhang ; T.M. Bachtiar ; W.K. Chou
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 144, Issue 1, p. 15 –21
- DOI: 10.1049/ip-cdt:19970960
- Type: Article
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A systematic approach for designing a fault-tolerant systolic array using space and/or time redundancy is proposed. The approach is based on a fault-tolerant mapping theory which relates space–time mapping and concurrent error detection techniques. By this design approach, the resulting systolic array is fault tolerant and achieves the optimal space–time product. In addition, it has the capability to compute more problem instances simultaneously without extra cost. - Author(s): C.-C. Chang and R.-J. Hwang
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 144, Issue 1, p. 23 –27
- DOI: 10.1049/ip-cdt:19970821
- Type: Article
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Cheating detection is a very important issue for threshold schemes. An efficient and simple cheating detection and cheater identification method is proposed in this paper. The attack of the proposed method is as difficult as factoring the product of two large prime numbers, the intractability of which forms the basis for RSA. The proposed method is more efficient than Wu et al.'s and Hwang et al.'s methods in the verification phase. In addition, this method can prevent a conspirator from falsely accusing any specific shadow-holder. - Author(s): T. Coffey and P. Saidha
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 144, Issue 1, p. 28 –32
- DOI: 10.1049/ip-cdt:19970838
- Type: Article
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A number of techniques based on logic theories have recently been developed to provide formal verification of security protocols. Many of these are based on logics of belief, which are considered useful in evaluating the trust which may be placed in a security protocol. Other techniques are based on logics of knowledge, which are suitable for proving protocol security. A new logic is proposed in the paper for formally analysing public-key protocols. The logic, which combines the logics of knowledge and belief, enables the analysis of the security and trustworthiness of a wide range of security protocols. Axioms are provided which express the low level properties of public-key protocols. These axioms can be combined, using inference rules, in attempting to deduce the desired goals for specific protocols. The paper presents the language syntax for the logic, and a description of the axioms and inference rules. An example of the use of the new logic, in analysing a well known peer-entity authentication protocol, is also described. - Author(s): A. Fuster-Sabater and P. Caballero-Gil
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 144, Issue 1, p. 33 –38
- DOI: 10.1049/ip-cdt:19970764
- Type: Article
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An efficient algorithm for computing lower bounds on the global linear complexity of nonlinearly filtered PN-sequences is presented. The technique here developed is based exclusively on the realisation of bitwise logic operations, which makes it appropriate for both software simulation and hardware implementation. The algorithm can be applied to any arbitrary nonlinear function with a unique term of maximum order. Thus, the extent of its application for different types of filter generators is quite broad. Furthermore, emphasis is on the large lower bounds obtained that confirm the exponential growth of the global linear complexity for the class of nonlinearly filtered sequences. - Author(s): K.-C. Wei ; B.-D. Liu ; J.J. Tang
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 144, Issue 1, p. 39 –42
- DOI: 10.1049/ip-cdt:19970636
- Type: Article
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An efficient method for EEPLA testing is presented. In this method the authors propose an interleave programming algorithm for the EEPLA to enhance the controllability of the OR plane and the observability of the AND plane during the testing of EEPLA. The salient features of this method are: (i) low overhead, (ii) high fault coverage, (iii) simple test set, and (iv) low test-application time. Using this method, all multiple stuck-at faults, multiple crosspoint faults and all multiple bridging faults can be detected. - Author(s): S.T.J. Fenn ; M. Benaissa ; D. Taylor
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 144, Issue 1, p. 43 –46
- DOI: 10.1049/ip-cdt:19970660
- Type: Article
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Two systolic multipliers for GF(2m) are presented, one bit-serial and one bit-parallel. Both multipliers are hardware efficient and support pipelining. Both architectures are highly regular, require only local communication lines and have longest delay paths independent of m. Consequently these multipliers can be clocked at high speeds and are suitable for VLSI implementation. The design of both these multipliers is also independent of the defining irreducible polynomial for the field. - Author(s): H.J. Tiersma
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 144, Issue 1, p. 47 –48
- DOI: 10.1049/ip-cdt:19970639
- Type: Article
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The use of more than one hard problem in the design of cryptographic protocols to enhance security has already been proposed. To this end, a way to embed the discrete logarithm problem as well as the factorisation problem in the signing process in the original El Gamal signature scheme has been described. It is shown that the described modification does not enhance the security of the original scheme.
Source level optimisation of VHDL for behavioural synthesis
Design and application of Parsim — a message-passing computer simulator
Optimal fault-tolerant design approach for VLSI array processors
Efficient cheater identification method for threshold schemes
Logic for verifying public-key cryptographic protocols
Global linear complexity analysis of filter keystream generators
Low test-application time method for EEPLA testing
Dual basis systolic multipliers for GF(2m)
Enhancing the security of El Gamal's signature scheme
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