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Volume 142
Issue 3
IEE Proceedings - Computers and Digital Techniques
Volume 142, Issue 3, May 1995
Volumes & issues:
Volume 142, Issue 3
May 1995
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- Author(s): P. Ramanathan and S. Chalasani
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 142, Issue 3, p. 177 –184
- DOI: 10.1049/ip-cdt:19951865
- Type: Article
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p.
177
–184
(8)
Solutions to partial differential equations are required in many engineering applications. The multigrid method is an iterative technique for speeding up the solution of these equations. The authors describe a parallel implementation of the multigrid method on the Connection Machine CM-5 architecture. An analytic model is presented for estimating the computation and communication times of the multigrid algorithm. The times predicted by the analytic model are within 5% of the results obtained from CM-5. Results demonstrate that the communication overhead incurred by the parallel multigrid algorithm is relatively small compared to the computation time. Consequently, implementations of the multigrid algorithm on the CM-5 easily achieve processor efficiencies near 100%. - Author(s): M.F. Lai ; M. Nakano ; Y.P. Wu ; C.H. Hsieh
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 142, Issue 3, p. 185 –192
- DOI: 10.1049/ip-cdt:19951790
- Type: Article
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p.
185
–192
(8)
Presents a VLSI architecture for clustering analysers. The proposed VLSI architecture exploits two-dimensional systolic arrays, which use a high degree of parallel and pipelined processing. The architecture dramatically reduces the immense number of processing elements which were required by previous architectures. Moreover, the same architecture can be utilised for applications with a variable number of input patterns. Also, unlike previous architectures, the patterns are applied to the inputs in a serial format, which can save a large number of pin counts, and therefore the proposed architecture is very attractive for VLSI implementation. Using the proposed architecture, the complexity of the VLSI circuit of the clustering analyser can be reduced significantly. - Author(s): C.-L. Wey
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 142, Issue 3, p. 193 –200
- DOI: 10.1049/ip-cdt:19951668
- Type: Article
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p.
193
–200
(8)
Presents a C-testable carry-free divider circuit design and its test generation. The divider circuit takes the dividend digits, in redundant binary form, and divisor digits, in binary form, as its inputs and produces the quotient and remainder digits, also in redundant binary form. The circuit is fully testable with a test set of 72 test patterns irrespective of its bit size. To generate the test patterns and the corresponding control signals easily, a graph labelling scheme is employed to derive a set of simple labels for the dividend, the divisor, the quotient, the remainder and the control signals. - Author(s): W.-H. Fang and J.-D. Lee
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 142, Issue 3, p. 201 –207
- DOI: 10.1049/ip-cdt:19951787
- Type: Article
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p.
201
–207
(7)
Presents two new linear systolic architectures for the 1D discrete Hartley transform (DHT). Both architectures exhibit several desired features such as regularity, modularity and high pipelineability, which make them amenable to VLSI hardware implementation. In addition, these new architectures use the CORDIC (Co-Ordinate Rotation DIgital Computer) algorithm as the basic function for each processing element, which has been shown to be an appealing approach to compute trigonometric functions. Combination of these two array processors to form a new fully pipelined mesh-connected systolic architecture for the 2D DHT is also addressed. This new architecture, which uses Horner's rule and the symmetric property of the transform by folding the data either in the time domain or in the frequency domain, yield higher throughput with reduced hardware complexity compared with other existing ones for both the 1D and 2D case. - Author(s): R. Venkateswaran and P. Mazumder
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 142, Issue 3, p. 208 –214
- DOI: 10.1049/ip-cdt:19951619
- Type: Article
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p.
208
–214
(7)
A new, highly parallel model for concurrent multilayer routing, called CHiRPS (Configurable Highly Routable Parallel System), is presented. The nucleus of CHiRPS is a very flexible pathfinder that can be easily configured, even in the presence of obstacles, to generate various commonly used pattern-based routes, such as Steiner trees with single trunk, comb trees, contour-based routes, etc., that span multiple layers simultaneously. The authors employ the concept of a total grid-graph to capture the state of the routing region. The main steps of the pathfinder are based on new parallel algorithms for cycle detection, cycle elimination and tree reduction. The proposed algorithms scale well with increased problem sizes since they require only O(log N) time when given a grid-graph with up to N2 nodes. As such, they are good candidates for massively data-parallel machines. - Author(s): A.A. Duncan and D.C. Hendry
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 142, Issue 3, p. 215 –224
- DOI: 10.1049/ip-cdt:19951789
- Type: Article
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p.
215
–224
(10)
COBRA (Column-Oriented Butted Regular Architecture) is a behavioural high-level synthesis tool for datapath-dominated applications. It globally optimises the synthesised datapath by performing the scheduling and allocation tasks simultaneously. COBRA uses a bit-sliced target architecture and layout style which, when compared with conventional approaches, significantly reduces the area of the final datapaths. The synthesis problem is formulated as an optimisation problem on the configuration of variable lifetimes when mapped into a 3D 'datapath space'. The configuration of the data in the datapath space implies the structure required to achieve the data configuration and hence the datapath. Simulated annealing is used to optimise the solution. A description is given of the target architecture, the mapping of the input description into the datapath space, the optimisation of the data configuration in the datapath space, and the post-processing operations. Results for a number of examples are presented. - Author(s): S.-S. Park ; C.-M. Kyung ; S.-H. Hwang
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 142, Issue 3, p. 225 –232
- DOI: 10.1049/ip-cdt:19951752
- Type: Article
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p.
225
–232
(8)
Presents a new, efficient algorithm for the state encoding of finite-state machines which minimises the area of the combinational logic. The encoding problem is modelled as the construction of a hypercube, where the encoding of each state is given by the co-ordinate of the corresponding vertex of the D-dimensional Boolean hypercube (D=log2(number of states)). The proposed state encoding scheme consists of computing the encoding affinities between states and placing states with strong encoding affinities closely in the hypercube. The algorithms are implemented as a program called SECH (State Encoding by Construction of Hypercube). Experimental results show that SECH yields more than 20% better results than NOVA (Villa et al., 1990) in a comparable CPU time, and about 10% better results than NOVA in about 1/200 of the CPU time. - Author(s): C.M. Krishna ; A. Ganz ; X. Wang
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 142, Issue 3, p. 233 –236
- DOI: 10.1049/ip-cdt:19951751
- Type: Article
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p.
233
–236
(4)
As distributed systems and computer networks become more sophisticated, the problem of accurately estimating the system traffic intensity increases in importance. Information about the traffic can be used, for example, by the network manager in load-dependent routing and system reconfiguration. This information can be gathered by carrying out window-based surveillance, i.e. traffic intensity is estimated by counting the packets transmitted over a window. The authors show how to compute the optimal window size if the traffic intensity parameter changes with time. - Author(s): L. Harn
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 142, Issue 3, p. 237 –240
- DOI: 10.1049/ip-cdt:19951874
- Type: Article
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p.
237
–240
(4)
Instead of using the conventional m-out-of-n perfect secret sharing scheme to protect a single secret among n users, the authors propose a secret sharing scheme based on one cryptographic assumption to protect multiple secrets. It is shown that, with this relaxation of the security requirement, secret sharing and some related secret-sharing problems, such as cheater detection and secret broadcasting, can be solved very efficiently.
Parallel multigrid algorithms on CM-5
VLSI design of clustering analyser using systolic arrays
Design and test generation of C-testable high-speed carry-free dividers
Efficient CORDIC-based systolic architectures for the discrete Hartley transform
CHiRPS: a general-area parallel multilayer routing system
High-level synthesis of DSP datapaths by global optimisation of variable lifetimes
Efficient state encoding algorithm based on hypercube construction
Window-based surveillance strategies
Efficient sharing (broadcasting) of multiple secrets
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