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IEE Proceedings - Computers and Digital Techniques

Volume 141, Issue 3, May 1994

Volume 141, Issue 3

May 1994

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    • Automated technique for high-level circuit synthesis from temporal logic specifications
      Design for testability of sequential circuits
      Unified approach to designing parallel Winograd algorithms
      Effect of nonuniform traffic on the performance of multistage interconnection networks
      Application of the CMAC input encoding scheme in the N-tuple approximation network
      Dual forms of Reed-Muller expansions
      Public-key cryptosystem design based on factoring and discrete logarithms
      Processor allocation strategies for modified hypercubes

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