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Volume 141
Issue 1
IEE Proceedings - Computers and Digital Techniques
Volume 141, Issue 1, January 1994
Volumes & issues:
Volume 141, Issue 1
January 1994
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- Author(s): H.G. Rotithor
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 141, Issue 1, p. 1 –10
- DOI: 10.1049/ip-cdt:19949630
- Type: Article
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System state estimation and decision making are the two major components of dynamic task scheduling in a distributed computing system. Combinations of solutions to each individual component constitute solutions to the dynamic task scheduling problem. It is important to consider a solution to the state estimation problem separate from a solution to the decision making problem to understand the similarities and differences between different solutions to dynamic task scheduling. Also, a solution to the state estimation problem has a significant impact on the scalability of a task scheduling solution in large scale distributed systems. The author presents a taxonomy of dynamic task scheduling schemes that is synthesised by treating state estimation and decision making as orthogonal problems. Solutions to estimation and decision making are analysed in detail and the resulting solution space of dynamic task scheduling is clearly shown. The proposed taxonomy is regular, easily understood, compact, and its wide applicability is demonstrated by means of examples that encompass solutions proposed in the literature. The taxonomy illustrates possible solutions that have not been evaluated and those solutions that may have potential in future research. - Author(s): P.-K. Ser and W.-C. Siu
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 141, Issue 1, p. 11 –16
- DOI: 10.1049/ip-cdt:19949876
- Type: Article
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By using the combination of the Hough and the contour sequence matching techniques, the authors suggest a new algorithm of scale and rotation invariant for pattern recognition. In the proposed algorithm, the conventional four-dimensional Hough space is replaced by a two-dimensional one. Because of the significant reduction of memory requirement, the authors can provide a much faster and more efficient generalised Hough algorithm. In order to enhance the performance of the Hough transform, they also suggest a new peak searching technique on the Hough space to achieve an accurate location of the detected objects. - Author(s): M.O. Esonu ; A.J. Al-Khalili ; S. Hariri ; D. Al-Khalili
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 141, Issue 1, p. 17 –28
- DOI: 10.1049/ip-cdt:19949816
- Type: Article
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A systematic approach to the design of fault-tolerant VLSI systolic arrays is proposed. The approach comprises three steps. First, redundancies are introduced at the computation level by deriving different versions of the computation structure. This involves the modification of the dependency matrix (D) of an algorithm to reflect a given fault-tolerance requirement. Second, the dependency matrix of the respective version is mapped into arbitrarily large size VLSI systolic arrays, using space-time (S-T) mapping techniques. Finally, a fault-tolerant (FT) systolic array is constructed by merging the corresponding systolic array of the different versions of the computation. The scheme is applicable to any systolic array implementation and suitable for VLSI technology. The method is illustrated using the matrix multiplication algorithm. - Author(s): T. Stouraitis
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 141, Issue 1, p. 29 –34
- DOI: 10.1049/ip-cdt:19949817
- Type: Article
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The performance of various interconnection networks (INs) is evaluated and compared. The throughput and complexity of the buffered and unbuffered Baseline IN (simple and augmented), in packet-switched environments, are compared with those of the crossbar, the (un)buffered BIN, and the single-buffered BIN. It is shown that adding buffers to a network improves its throughput. It is also shown that augmentation improves the performance of a network more than buffering does for networks with up to seven stages, whereas buffering is recommended for larger networks. - Author(s): Md.N. Karim and A. El-Amawy
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 141, Issue 1, p. 35 –39
- DOI: 10.1049/ip-cdt:19949821
- Type: Article
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In a large-scale multiprocessing system, contention for a particular memory location (called hotspot), may create congestion in the interconnection network. Usually a tree of saturated buffers rooted at the hot memory module and extending to the processors is formed which causes excessive delay for both hotspot and regular nonhotspot requests. To prevent tree saturation, a simple combining technique is proposed. The technique attempts to increase the chances of request combining. The new scheme called input queue combining uses simpler queueing structure compared to those proposed for conventional pairwise combining. The component count in each queue reduces to one-third of that in pairwise combining and the number for the waitbuffer reduces to half. While conventional pairwise combining is effective only for smaller networks, the proposed technique eliminates tree saturation even in very large networks, with reasonable delay. Networks delays reported here are among the lowest reported to date. - Author(s): S. Nandi ; B. Vamsi ; S. Chakraborty ; P. Pal Chaudhuri
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 141, Issue 1, p. 41 –47
- DOI: 10.1049/ip-cdt:19949812
- Type: Article
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Two-patterns are required to test single stuck-open faults in CMOS circuits, while detection of multiple stuck-open faults requires the application of three-patterns. The regular, modular and cascadable structure of cellular automata (CA) has been proposed as a built-in self-test (BIST) structure for on-chip generation of two-pattern and three-pattern test vectors. An analytical tool has been developed to characterise the properties of CA as a test pattern generator for CMOS circuits. The conditions to generate exhaustive two-patterns and three-patterns of n-bits have been investigated. Based on matrix algebraic analysis, it is shown that a specific class of CA satisfying this condition can be employed as a BIST structure for testing CMOS circuits. A lower bound on CA size has been analytically established. Criteria for the selection of the most desirable CA structure have also been presented along with the experimental results for a set of real-life circuits. - Author(s): R. Byrne and G.C. Shoja
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 141, Issue 1, p. 49 –56
- DOI: 10.1049/ip-cdt:19949891
- Type: Article
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A distributed algorithm for solving the symbolic compaction problem based on the virtual grid approach is presented. The distributed layout compaction system (DLCS) is an implementation of this algorithm. The symbolic compaction problem consists of translating a symbolic description of a VLSI layout into the smallest possible mask level description without violating any design rule. The distributed algorithm follows the client/server model. Client/server communication is provided by remote procedure calls (RPC) and modified RPCs, that allow parallel computations. The client is responsible for partitioning the layout problem into separate regions to be compacted by a set of server processes, and for merging these separately compacted regions into the final mask descriptions. The partition strategy is shown to allow effective parallelism of the compaction problem. DLCS was tested using a standard set of symbolic compaction benchmarks. - Author(s): T. Hwang and J.L. Chen
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 141, Issue 1, p. 57 –60
- DOI: 10.1049/ip-cdt:19949890
- Type: Article
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p.
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Two new ID-based conference key broadcast systems are proposed. The conference key can be distributed knowing only the receivers' identities. Only one copy of the ciphertexts is required to broadcast to all users. The security of these new schemes is based on the difficulty of factorisation as well as computing the discrete logarithm. We investigate their security and give a comparison to a recently proposed scheme. - Author(s): J.-W. Kang ; P.D. Fisher ; C.-L. Wey
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 141, Issue 1, p. 61 –64
- DOI: 10.1049/ip-cdt:19949889
- Type: Article
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A model and procedure are developed for synthesising asynchronous sequential logic elements (ASLEs). This model represents the functional behaviour with a more compact form, and the procedure can synthesise them more efficiently than the traditional one. With the delineation of inputs as mode inputs,level inputs and edge inputs from the design specification, a set of equations can be generated which describes the logic module's functional behaviour. The calculated states from these equations have bipartite adjacency relationships, which can easily be mapped onto an n-cube to obtain race-free state assignments. This procedure can also be applied for the synthesis of an asynchronous sequential logic circuit (ASLC) which has many data inputs and a small number of control inputs.
Taxonomy of dynamic task scheduling schemes in distributed computing systems
Non-analytic object recognition using the Hough transform with the matching technique
Fault-tolerant design methodology for systolic array architectures
Performance evaluation of BIN/ABIN networks in buffered/unbuffered packet-switched environments
Preventing tree saturation in multistage networks
Cellular automata as a BIST structure for testing CMOS circuits
Distributed system for VLSI layout compaction
Identity-based conference key broadcast systems
Efficient modelling and synthesis procedure of asynchronous sequential logic elements
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