IEE Proceedings - Circuits, Devices and Systems
Volume 153, Issue 4, August 2006
Volumes & issues:
Volume 153, Issue 4
August 2006
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- Author(s): Z. Ghassemlooy and S.S. Dlay
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 4, p. 289 –291
- DOI: 10.1049/ip-cds:20069018
- Type: Article
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p.
289
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- Author(s): J. Wu and T. Srikanthan
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 4, p. 292 –298
- DOI: 10.1049/ip-cds:20050273
- Type: Article
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p.
292
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Reconfigurable techniques attempt to realise maximum possible fault-free sub-arrays in mesh connected VLSI arrays with faulty elements. Although this problem has been investigated extensively, the performance of the resulting sub-arrays has not been addressed fully. In this paper, techniques for finding the high performance target array (HPTA) in the given VLSI array are proposed. First, it is shown that finding an HPTA in the given VLSI array is equivalent to solving a typical optimisation problem of multistage decision. Then a heuristic algorithm is presented based on dynamic programming for an HPTA. The proposed algorithm minimises the interconnect length of the target array by revising each original logical column to the optimal one without sacrificing on the size of the sub-array. Simulation results conclusively show that the proposed algorithm reduces the number of long interconnects in the sub-array without loss of harvest. - Author(s): B. Ontiveros ; I. Soto ; R. Carrasco
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 4, p. 299 –306
- DOI: 10.1049/ip-cds:20050117
- Type: Article
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p.
299
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The construction of an efficient cryptographic system, based on the combination of the ElGamal elliptic curve algorithm and convolutional codes using the Viterbi decoding algorithm over the Gaussian channel, is proposed. The originality is based on the construction of the mapping of encryption and coding at the channel level and the constraints imposed on the construction of the elliptic curve. When using elliptic curves and codes for cryptography it is necessary to construct elliptic curves with a given or known number of points over a given finite field with a range of constraint lengths, in order to represent the input alphabet and produce channel gain, respectively. The results show that the benefit of coding with encryption increases the security and coding gain and reduces the expansion factor, but at the expense of higher complexity. - Author(s): G.R. Mohammad-Khani ; G. Ferre ; J.P. Cances ; V. Meghdadi ; J.-M. Dumas
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 4, p. 307 –314
- DOI: 10.1049/ip-cds:20050169
- Type: Article
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p.
307
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A generalised framework for the maximum likelihood decoding of STBC is proposed. Using algebraic tools, a new matrix model particularly well suited to the description of MIMO systems is derived. After giving their particular detection rules the authors determine a new accurate upperbound for the BER performance of STBC transmitting schemes. Performance results are given which show the accuracy of the derived upperbound. - Author(s): U. Speidel
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 4, p. 315 –319
- DOI: 10.1049/ip-cds:20050168
- Type: Article
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p.
315
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In 1995, Nicolescu and Titchener showed that every finite string could be used to generate a unique recursively constructed variable-length code set belonging to the family of the T-codes. The present paper shows how this duality may be exploited to assess the randomness of strings and provide guidance in the construction of pseudo-random strings. - Author(s): L.C. Khor
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 4, p. 320 –331
- DOI: 10.1049/ip-cds:20050258
- Type: Article
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p.
320
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In general, existing blind source separation (BSS) algorithms have been designed based on assumptions that there are at least an equal number of sources and sensors and/or there is no noise present. These ideal situations rarely exist and hence the algorithms do not produce optimum results where either one or both of the assumptions have been violated. Underdetermined mixtures where the number of source signals is greater than the number of observed signals are encountered in neural signal detection from a small number of sensors, image modelling, EEG data and biomedical applications. A new algorithm to estimate unknown source signals from fewer observed signals and simultaneously reduce noise is proposed. The proposed algorithm is based upon a model that addresses the issue of noise and offers greater accuracy with standard assumptions relaxed. It offers an attractive solution with no pre-requisites on the nature of the signals and noise for the algorithm to be applicable. Most BSS algorithms adopt batch processing and are only applicable to orthogonal mixtures. The proposed algorithm does not require the mixing matrix to be orthogonal and can be implemented in an adaptive format to track time-varying mixtures. Results supporting the algorithm's superiority and comparisons with results from other algorithms are also presented to prove the tracking capability of our adaptive algorithm. Synthetic and real-time simulations demonstrate the improvement in convergence and accuracy of estimated signals with fewer restrictions in terms of its applicability. - Author(s): P. Gao ; W.L. Woo ; S.S. Dlay
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 4, p. 332 –345
- DOI: 10.1049/ip-cds:20050252
- Type: Article
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p.
332
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This authors develop a novel technique for blind source separation (BSS) of nonlinearly mixed signals. A new type of nonlinear mixture is derived where a linear mixing matrix is slotted between two layers of multiple mutually inverse nonlinearities. The paper discusses the separability of this new mixing model within the BSS context. This model further culminates to a framework where the separation solution integrates the theory of series reversion with the Weierstrass neural network and the hidden neurons are spanned by a set of mutually inversed activation functions. Simulations have been undertaken to support the theory of the developed scheme and the results indicate promising performance. The proposed method outperforms other tested algorithms in recovering both synthetic and the real-life recorded signals. The method of selecting the optimum order of the Weierstrass series has also been derived and implemented to balance the computational complexity and the accuracy of signal separation. - Author(s): T. Chalvatzis ; E. Gagnon ; J.S. Wight
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 4, p. 346 –350
- DOI: 10.1049/ip-cds:20050154
- Type: Article
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p.
346
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The effect of clock jitter on sampling systems is investigated. Analytical expressions are derived for the signal-to-noise ratio (SNR) of an ideal analogue-to-digital converter (ADC). The SNR expressions are based on the autocorrelation function properties of stationary random signals. The power spectral density (PSD) of the analysed signals is baseband/bandpass rectangular and bandpass raised cosine. System level simulations show that the SNR depends on the signal frequency rather than the bandwidth for direct RF and IF sampling. Special focus is given to direct sampling systems with raised cosine PSD (IS-95) in the presence of a blocking signal. - Author(s): T. Radvánszki ; B. Benkovics ; S. Imre
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 4, p. 351 –356
- DOI: 10.1049/ip-cds:20050165
- Type: Article
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p.
351
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The recently emerging possibility of ubiquitous wireless connectivity has increased the importance of the effective radio bandwidth usage. In the case of distributed multiple access MAC algorithms are needed that lower the probability of collisions. The authors focus on a new wireless medium access procedure that aims to increase the efficiency of the radio bandwidth usage. The presented VTBM (virtual transmission based MAC) procedure is based on the dynamic p-persistent algorithm and uses a virtual transmission mechanism. Simulation results presented demonstrate that the proposed algorithm outperforms the exponential backoff algorithm used in 802.11 DCF MAC regarding throughput and collision rate. - Author(s): C.Y. Chee and D. Xu
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 4, p. 357 –360
- DOI: 10.1049/ip-cds:20050139
- Type: Article
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p.
357
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We propose a chaos-based communication technique for transmitting M-ary digital signals using controlled projective synchronisation of a coupled chaotic system. This development shifted chaos-based digital communication to truly M-ary transmission where the communication system can transmit digital symbols that consist of more than one bit and thus allow faster transmission rate without increasing the system complexity. The proposed technique is proven by numerical simulation results to be superior over conventional and other chaos-based digital communication techniques in terms of bit error rate at low Eb/N0. - Author(s): Z. Ghassemlooy ; W.P. Ng ; H. Le-Minh
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 4, p. 361 –369
- DOI: 10.1049/ip-cds:20050238
- Type: Article
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p.
361
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In future high-speed self-routing photonic networks based on all-optical time division multiplexing (OTDM) it is highly desirable to carry out packet switching, clock recovery and demultiplexing in the optical domain in order to avoid the bottleneck owing to the optoelectronics conversion. We propose a self-routing OTDM node structure composed of an all-optical router and a demultiplexer based on the symmetric Mach–Zehnder (SMZ) for high bit rate OTDM packets. Here, we investigate both numerically and by means of simulation the noise and crosstalk characteristics of the SMZ and the bit error rate (BER) performance of the proposed OTDM node. For BER of 10−9 and the total bit rates of 100 and 200 Gbit/s the power penalty incurred is about 2 and 2.5 dB, respectively compared with a 2.5 Gbit/s back-to-back (B-B) system. - Author(s): P. Huang and A.C. Boucouvalas
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 4, p. 370 –374
- DOI: 10.1049/ip-cds:20050156
- Type: Article
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p.
370
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Proposed by IrDA, the Infrared Simple Connection (IrSC) protocol is a protocol dedicated for fast connection and instant data transmission over point-to-point infrared links. Although the protocol is still under development, it has attracted considerable attention from both manufacturers and researchers. The IrDA special interest group proposed two different technical approaches to address the requirements of IrSC. In this paper, technical approach 1 (IrSC1) and approach 2 (IrSC2) are modelled. Subsequently, the performance of IrSC1 and IrSC2 is compared. Additionally, the performance of unchanged IrDA Standard (IrDAS) is compared with both approaches. The contribution of this work is to clarify the issues for designing IrSC, and compare IrSC1 and IrSC2, in addition to providing suitable design guidelines for IrDA devices for high performance of IrSC.
Editorial: Communication systems, networks and digital signal processing
Reconfiguration of high performance VLSI sub-arrays
Construction of an elliptic curve over finite fields to combine with convolutional code for cryptography
Derivation of accurate upperbounds for STBC maximum likelihood decoding
Constructing finite pseudo-random strings using codeset-based entropy measures
Robust adaptive blind signal estimation algorithm for underdetermined mixture
Weierstrass approach to blind source separation of multiple nonlinearly mixed signals
Clock jitter in direct RF and IF sampling wireless receivers
Virtual transmission based MAC protocol for wireless access
Chaos-based M-ary digital communication technique using controlled projective synchronisation
BER performance analysis of 100 and 200 Gbit/s all-optical OTDM node using symmetric Mach–Zehnder switches
Modelling IrSC: proposal options and performance analysis
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- Author(s): R. Mita ; G. Palumbo ; M. Poli
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 4, p. 375 –382
- DOI: 10.1049/ip-cds:20050314
- Type: Article
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p.
375
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A novel stream cipher based on the popular linear feedback shift register (LFSR) with a dynamic feedback network controlled by a decoder circuit is presented. The proposed circuit can be employed efficiently in cryptographic applications owing to its improved inviolability property compared to traditional LFSRs. Indeed, although the proposed topology and traditional LFSRs have similar statistical properties, it exhibits a very high linear complexity (LC) and the sequences generated from the novel topology are much more difficult to be predicted. The proposed cipher is described and design criteria to choose the key of the system are also given. As an example, a 16-bit length generator was implemented on a Xilinx FPGA and experimentally verified using the most common statistical and randomness tests. Then it was also designed in standard cell AMS technology. Moreover, to test the generator's inviolability, a novel methodology, based on a multi-perceptron neural network, was also developed and is also presented. - Author(s): J. Wu and T. Srikanthan
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 4, p. 383 –389
- DOI: 10.1049/ip-cds:20045103
- Type: Article
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p.
383
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The reconfiguration process within fault tolerant systems must be accelerated for the rapid generation of degradable VLSI arrays. Given an m×n mesh-connected VLSI array with faulty density ρ, finding an m′×n′ fault-free sub-array under the row and column rerouting such that m′≥r and n′≥c for integers r and c, has been shown to be NP-complete. In this paper, we propose efficient heuristic techniques based on partial rerouting strategy. We show that by enhancing popular logical row exclusion and the greedy column rerouting techniques, we reduce the routing time from O(max(m−r, n−c)·(1−ρ)·m·n) to O(β·(1−ρ)·m·n), where β≪max(m, n), without loss of harvest. Simulations based on a range of square arrays and fault densities conclusively show that the computation time can be improved by more than 70% for a fault density of 10%. Moreover, performance improvement of up to 98% is noted when the fault density is reduced to 0.1%. - Author(s): S. Chun ; Y. Kim ; M.-H. Yang ; S. Kang
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 4, p. 391 –398
- DOI: 10.1049/ip-cds:20050307
- Type: Article
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p.
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The proposed scheme, called the IOC-LP (input reduction and one block compression for low power test), compresses the test data of scan based SoCs to improve the compression ratio in the ATPG process. It does so by using the modified input reduction and novel techniques, a new scan flip-flop reordering for low power test, the newly proposed one block compression, and a novel reordering algorithm. Unlike previous approaches using the cyclic scan register architecture, the proposed scheme is able to compress original test data and to decompress the compressed test data without the cyclic scan register architecture. Therefore, the proposed method leads to a better compression ratio with lower hardware overhead and lower power consumption than previous works. Experimental results on ISCAS '89 and ITC '99 benchmark circuits validated the proposed method. - Author(s): C.-Y. Lee ; C.W. Chiou ; A.-W. Deng ; J.-M. Lin
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 4, p. 399 –406
- DOI: 10.1049/ip-cds:20050188
- Type: Article
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p.
399
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Cryptographic applications based on finite fields have recently attracted considerable interest. This work develops two new algorithms, called the time-dependent and time-independent multiplication algorithms, for computing A(x)B2(x) over a finite field GF(2m) using an interleaved conventional multiplication approach. The proposed algorithms allow efficient realisation of the bit-parallel multiplication using iterative arrays. The results reveal that our proposed time-dependent and time-independent multipliers save approximately 34% and 62% less space complexity, respectively, compared to the traditional multipliers for a general polynomial basis of GF(2m). Additionally, the presented multiplication algorithms can also be effective Montgomery multiplication algorithms to yield low-complexity architectures.
Pseudo-random sequence generators with improved inviolability performance
Accelerating reconfiguration of degradable VLSI arrays
IOC-LP: hybrid test data compression/decompression scheme for low power testing
Low-complexity bit-parallel systolic architectures for computing A(x)B2(x) over GF(2m)
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