Parallel changes, in which separate lines of development are carried out by different developments, are a basic fact of developing and maintaining large-scale software systems. Merging parallel versions and variants of source code is a common and essential software engineering activity. When a non-trivial number of conflicts is detected, there is a need to support the maintainer in investigating and resolving these conflicts. In this study, the authors present software conflict resolution recommender (scoreRec), a cost–benefit approach to ranking the conflicting software entities. The contributions of scoreRec lie in the leverage of both structural and semantic information of the source code to generate conflict resolution recommendations, as well as the hierarchical presentation of the recommendations with detailed explanations. The authors evaluate scoreRec through an industrial-strength legacy system developed by computational scientists. The results show that scoreRec offers relevant and insightful information and sound engineering support for conflict resolution. The authors' work also sheds light on the future development of recommendation systems in the context of software merging.

Unified modelling language (UML) is a visual modelling language, which has gained popularity among software practitioners. In a model-driven software development environment, the existing UML tools mainly support automatic generation of structural code from UML class diagrams. However, the code generation from UML diagrams such as statechart, activity, collaboration and sequence diagrams (SDs) are not supported by most UML tools and also have scarcely been reported in the literatures. This work proposes an approach to automatic generation of code from UML 2.x SDs of use cases. From the XML metadata interchange (XMI) representation of an SD of a use case, the authors construct a graph model called sequence integration graph (SIG). The SIG encapsulates information related to messages, control flow and method scope of interactions. These information are then used to generate code. The proposed approach has been tested using a number of real-life application systems and the results substantiate the efficacy of the approach to synthesise the code for controller classes. The authors observe that approximately 48% of the total lines of code within controller class methods can be generated with the proposed approach. The proposed approach can be easily extended to other behavioural UML models such as interaction-overview diagrams, communication diagrams and activity diagrams.

The authors propose a state-based risk assessment methodology at the analysis and design stage of Software Development Life Cycle. First, a method is proposed to estimate the risk for various states of a component within a scenario and then, the risk for the whole scenario is estimated. The key data needed for risk assessment are complexity and severity. An Inter-Component State-Dependence Graph is introduced to estimate the complexity for a state of a component within a system. The severity for a component within a scenario is decided based on three hazard techniques: Functional Failure Analysis, Software Failure Mode and Effect Analysis and Software Fault Tree Analysis. The risk for a scenario is estimated based on the risk of interacting components in various states within the scenario and State COllaboration TEst Model of the scenario. Finally, the system risk is estimated based on two inputs: scenarios risks and Interaction Overview Diagram of the system. The methodology is applied on a Library Management System case study. An experimental comparative analysis is performed and observed that the testing team guided by our state-based risk assessment approach achieves high test efficiency compared with it with an existing component-based risk assessment approach.

As the process tailoring is an inevitable and costly activity in software development projects, it is important to reduce the effort for process tailoring. It is critical to a large-sized software process. A large-sized software process usually contains hundreds of elements and relationships between the elements. Manually identifying the elements to be tailored is laborious and error-prone. To overcome this problem, the authors proposed an approach to process tailoring using process slicing (PS) in a large-sized software process. PS operates on a software process that includes various sub-processes and utilises past experience by case-based reasoning (CBR) technique to increase its effectiveness. The authors validated that PS can help a project manager to identify the elements to be tailored with less effort. It has also been illustrated that the CBR technique is helpful in reducing errors and increasing the performance of PS.

The challenges in silicon testing and debug of complex integrated circuits are well understood. Where these circuits include multiple processor cores there is also a dramatic increase in the complexity of verifying and debugging the associated software; with much of this complexity being because of the inherent lack of visibility over internal signals which integration brings. The trend to-date has been to rely upon silicon test interfaces to provide access to internal signals required for software verification and debug. However, it is questionable whether this is sufficient for real-time systems or future designs with increasing processor cores. This study examines the on-chip technology supporting software verification and debug in current designs and proposes enhancements in this area. As much of this technology is primarily intended for silicon test it is lacking in terms of I/O bandwidth, which is a significant limitation for software verification and debug. The authors propose their alternative approach of using an on-chip coprocessor and debug circuitry to address this principal limitation; and describe an embedded application where this approach was successfully applied to monitor timing requirements and detect failures. The authors also outline how this approach could be applied as an architectural solution for formal runtime verification.