This study presents a new coupled inductor magnetic structure with variable coupling coefficient. The new symmetrical magnetic structure is composed of stacked ferrite cores, where control legs are placed in the centre of the core structure, on equal distances from the outer legs. In that way, the coupling coefficient is controlled by the means of a DC current. The DC control flux is confined only to the control legs and it is equally balanced in both of the outer legs. Distribution of the control DC flux in the proposed structure is verified applying finite element analysis simulation of the three-dimensional model. Electrical properties of the new variable coupled inductor are derived applying analytical modelling and verified by experiments. Maximal variations of the controlled coupling coefficient value in respect to the different value of the leakage flux are obtained and presented. Design and experimental results are presented for application in an interleaved boost converter with a variable coupled inductor, achieving boundary conduction mode over a wide load variation.

In the multi-terminal flexible dc grid, it is important for the healthy network to ride through the dc fault. The converters should operate continuously after dc faults, staying unblocked. But the existing selective protection and isolation method may fail to react swiftly enough, because the propagation speed of the dc fault current is extremely fast. This paper discussed the fault current limiting requirements and proposed a calculation method to determine the required dc reactor value, for the purpose of the converter continuous operation during dc faults. On this basis, the bridge-type fault current limiter (FCL) was proposed for using in the dc grid, due to merits including minor negative influence on dc grid normal operation, fast response to dc faults and efficient coordination with the dc circuit breaker (DCCB). The parameter design principle of the bridge-type FCL for dc grid was also discussed. Then the scaled-down dc experiment test circuit was built to verify the working principle and performance of the bridge-type FCL. Finally, the simulation cases based on the PSCAD/EMTDC were carried out to verify the feasibility of the theoretical calculation method and the superiority of the proposed bridge-type FCL for using in the dc grid.

The introduction the full-SiC (full silicon carbide) high power modules in the power semiconductors market makes necessary the development of new gate drivers suitable for its switching characteristics. The design considerations, challenges and implementation for high power SiC metal–oxide–semiconductor field-effect transistors is presented in this study. Aspects like voltage clamping, overcurrent/short-circuit protection, different power supply voltage levels, gate circuit and soft off-switching are addressed, considering the particularities that must be managed with SiC devices, like stray inductance and oscillations in switching transitions. All the gate drivers parts are designed without using programmable elements, that increase the complexity and cost of the gate driver design. Experimental results of the gate driver behaviour are also presented to validate the design. The approach proposes a modular gate driver divided into two parts. Firstly, a base driver (BD) board that depends on the electrical characteristics of the SiC module. Secondly, a core driver (CD) board, which can be considered ‘universal’ for any SiC power module with the same voltage operation level. For experimental validation, the proposed gate driver (BD + CD boards) is tested in two different power converters: a 50 kVA DC–AC inverter and a 100 kVA interleaved DC–DC converter.

The dead-time effect is observed in the three-phase dual-active bridge (DAB) DC/DC converter. The occurrence of the dead-time effect depends on the relationship of the switching frequency, the phase shift value, the dead-time value and the equivalent conversion ratio. The dead-time effect may have a significant impact on the converter performance when high switching frequency, wide input and output voltage range or wide operation power range are required. Therefore, comprehensive research of the dead-time effect is essential to improve the design of the three-phase DAB converter over a wide operation range. In this study, all the cases of the dead-time effect in the three-phase DAB converter are analysed in terms of the buck, boost, and matching states. The expressions of the transmission power, constraint conditions, and key time of the dead-time effect are derived for each state. The operation waveforms of the dead-time effect are also presented to better understand the dead-time effect. Finally, the analysis is verified by both simulation and experimental results.

The presence of direct current (DC) offset and harmonics–interharmonics (HIHs) in grid voltage input signal of phase-locked loop (PLL) results in inaccurate controller response. The inaccuracies are due to the low- and high-frequency oscillations that appear in the PLL estimated phase, amplitude and frequency. The suppression of fundamental frequency oscillations caused by DC offset (DO) in the input voltage signal must be carried out without compromising the dynamic response of the system. The use of low-pass filters, for example, results in undesirable, slow response. This study proposes an accurate and fast decoupling of fundamental frequency oscillations using a mathematic-cancellation decoupling cell. Higher-frequency oscillations generated by HIHs are eliminated by a different harmonic compensation network (HCN) that is also proposed in this study. The performance of conventional techniques is limited because they eliminate only specifically selected harmonics. The proposed PLL, however, eliminates any number of HIHs present in the grid with the least computational complexity and without any prior knowledge. Furthermore, its advanced features provide accurate synchronisation under any abnormal grid condition at the lowest computational complexity when compared with the existing state-of-the-art PLLs. The advanced performance of the proposed HIHDO-PLL is verified through simulation and experimental results.

This work presents a multi-input converter (MIC) that can build a DC microgrid having renewable energy resources, balanced sources, and energy storage devices. After analysing its operation modes, a design procedure for the converter considering three different cases is provided. This procedure includes the semiconductor elements selection and design of the inductors. After this step, a detailed efficiency analysis is carried out for the studied cases. Finally, a 1 kW prototype creating a photovoltaic–battery system is built. Through several experiments based on this set-up, it is shown that the theoretical analysis is accurate and the studied MIC can be successfully utilised to create DC microgrid.

The robust operation of grid-connected converters under non-ideal grids is a challenging topic. Synchronising of converters requires accurate estimation of the grid vector angle which is traditionally performed by phase locked loops (PLLs). Separating the grid voltage and current sequence components is essential for controlling converters under non-ideal grids. In this study, an efficient method to separate the grid sequence components using cascaded delayed signal cancellation (CDSC) is developed. The proposed method is a reduced version of the conventional delayed signal cancellation separation technique. Implementing CDSC in the stationary frame enables for using a higher bandwidth without degrading its filtering capability which enables for using the GSS as a pre-filter stage for the traditional synchronous reference frame PLL. Therefore, the obtained grid sequence separator PLL (GSS-PLL) accurately estimates the grid vector angle under severe conditions. The performance of GSS method as well as GSS-PLL is compared to the conventional multiple second-order generalised integrator (MSOGI) method under unbalance, phase interruption and harmonically distorted grids. The accuracy of the proposed method is verified through simulation and experimental tests. The low computational effort of GSS scheme compared to the MSOGI is a significant advantage which encourages its implantation for most of the grid-connected converters.

Wireless power transfer (WPT) has attracted a large amount of attention due to its inherent advantages such as convenience, safety, low maintenance, weather proof and so on. Compensation topology is crucial for WPT system due to its function of reducing reactive power and improving system efficiency. Series–series (SS) compensation topology is widely employed due to a simple structure and the characteristic of constant current output (CCO). However, it has three serious drawbacks: high-voltage stresses on compensation capacitors, poor CCO characteristic under practical situations and significant dependence on coupling coils. This study proposes LC/CL (primary inductor–capacitor and secondary capacitor–inductor) compensation topology to eliminate aforementioned deficiencies of SS. The voltage stresses on compensation capacitors of LC/CL are much lower than those of SS. LC/CL also provides better CCO characteristics in imperfect scenarios. Load current of LC/CL compensated system only increases by 1.89% when the load is reduced by half. In contrast, the load current of SS compensated system increases by 6.87% with identical load reduction. An efficiency-based optimisation method is proposed for higher end-to-end efficiency as well. The validity of the optimisation is justified by both simulation and experiment. The efficiency of the optimised system is about 2% higher than that of a non-optimised system.

The filtering performance of series hybrid active power filter (SHAPF) based on fundamental magnetic flux compensation positively correlates with the magnetising impedance of the transformer. However, excessive magnetising impedance will decrease reliability while increasing capacity and costs of the whole system. In order to reduce the magnetising impedance while ensuring the same filtering performance of SHAPF, an improved series active power filter (ISAPF) with fundamental and harmonics magnetic flux hybrid control is presented here. The equivalent impedances to fundamental and harmonics in ISAPF are firstly analysed to explain the principle of ‘harmonic isolation’. Then the range of compensation coefficients is investigated in detail based on the complete control block diagram and the open-loop function of ISAPF. Moreover, stability conditions of an overall system with non-linear loads are deduced. Finally, a set of single-phase prototype with two kinds of special transformer has been constructed; the related experiments results showed that ISAPF can ensure the filtering performance while applying a transformer with smaller capacity, thus resulting in the reduction in capacity and the costs while increasing the reliability.

Compared with the traditional cascaded H-bridge multi-level inverters, the hybrid cascaded multi-level inverters have been receiving attention because they can generate more levels with the same number of power cells. However, with the general hybrid pulse width modulation (PWM), the output power distribution between the high-voltage and low-voltage H-bridge cells is extremely uneven in low amplitude modulation, and it may appear that the high-voltage cell feeds power into the low-voltage cell in some modulation ratio intervals causing the low-voltage cell capacitor voltage boost. To avoid this problem, a method of a modified hybrid PWM strategy with power balance control is proposed. It has achieved the output power balance of H-bridge cells in full amplitude modulation, the occurrence of the phenomena of extremely uneven output power distribution between the high- and low-voltage cells in low amplitude modulation is avoided, and the performance of the inverter is improved. Simulation and experimental results verify the correctness and feasibility of the proposed strategy.

Digital implementation of current-mode control (CMC) considers the outer voltage-loop in the digital domain, whereas the inner current-loop is kept either in the analogue domain in mixed-signal CMC (MCMC) or in the digital domain in fully digital CMC (DCMC). Under finite voltage-loop sampling, this study reports that the selection of sampling point can completely change the stability status of a boost converter with non-minimum phase behaviour, particularly in the presence of the effective-series-resistance of the output capacitor. A discrete-time framework is proposed for fast-scale stability analysis in a boost converter, operating under continuous conduction mode. Further, discrete-time small-signal models are derived and design guidelines are proposed for both MCMC and DCMC architectures with enhanced stability for fast transient performance. Keeping in mind software-controlled DCMC, a considerably large sampling delay is considered, and its effect on the performance and stability is discussed. A boost converter prototype is tested and various DCMC schemes along the proposed design techniques are implemented using a field-programmable-gate-array device.

This paper proposes an analytical expression for the calculation of active and reactive power references of a grid-tied inverter, which limits the peak current of the inverter during voltage sags. The key novelty is that the active/reactive power references are analytically calculated based on the dc-link voltage and grid codes, while they do not depend on the implemented current reference calculation algorithm and, as a general formulation, can be implemented in combination with various current reference calculation algorithms. Furthermore, based on the inverter nominal current and the injected reactive power to the grid during voltage sags, an analytical algorithm is introduced for the calculation of the active power reference, which can be extracted from PV strings. The proposed algorithm ensures that the maximum current capability of the inverter is used for the enhancement of the grid voltages during voltage sags, while it always complies with the reactive power injection requirement of grid codes and avoids increasing the dc-link voltage excessively. An unbalanced current injection algorithm is also applied for the grid-tied inverter which results in zero active power oscillation. Experimental results of a grid-connected 3.3-kVA, three-level, neutral-point-clamped inverter laboratory prototype are presented to demonstrate the effectiveness of the proposed controller.

A large amount of ripple at twice the output frequency will emerge in the input current due to the pulsating output power in a single-phase inverter. A current-fed-type single-stage single-phase inverter is investigated. Based on the switch multiplexing technique, it can realise not only dc–ac power conversion but also low-frequency input current ripple reduction with a lower number of power switches. A control strategy is proposed, which is capable of controlling both the input and output port performance. The operation performance is analysed, including circuit parameters, efficiency and dynamic behaviour. Besides, the equivalence of control strategy and the similarity of circuit component rating are revealed between this single-stage inverter and a conventional two-stage inverter. The single-stage inverter is preferred in the applications which are sensitive to the power switch number and low-frequency input current ripple. Finally, some experimental results are performed to verify the theoretical analysis.

In this study, a new structure is proposed for non-isolated boost dc–dc converters using voltage-lift technique. The increasing voltage gain in the proposed converter is achieved step-to-step by a simple structure. In the proposed converter, there is a direct connection to an inductor in input side which provides free current ripple for the input source. Here, the proposed converter performance analysis and their relations are presented in continuous conduction mode and discontinuous conduction mode as well as voltage gain equations for each mode in detail. Then, switching current stress equations in each mode and critical inductance equations are extracted for design considerations. Finally, the carried theoretical analysis and satisfying operation of the proposed converter are verified via experimental results of laboratory prototype.

This study proposes a modular high voltage gain structure for non-isolated non-coupled inductor based multi-input (NINCIBMI) dc–dc converters. Proposed topology can produce higher voltage gains per number of components (switch, diode, capacitor and inductor) than other NINCIBMI topologies. In other words, the proposed topology uses less number of components for achieving the same voltage gain. This property can lead to reduced cost, size, weight and complexity of topology. Also, proposed topology benefits from continuous input current. Despite the high voltage gain of proposed topology, it has considerably low normalised voltage stress (NVS) on its switches/diodes. Another important advantage of proposed topology is that, as the number of input units increase, the voltage gain increases too, but the NVS on switches/diodes decreases. The proposed topology is suggested for low and medium power applications. The 2-input version of proposed topology has been studied in detail and different operational modes and steady-state analyses have been presented. For a better evaluation, proposed topology has been compared with recently presented novel multi-input high step-up structures. The 2-input version has also been experimentally implemented. Obtained results confirm appropriate performance of proposed topology.

This study presents a new method of switching angle solution based on composite differential evolutions (CoDE) in selective harmonic mitigation pulse width modulation (SHMPWM). The method can effectively improve the global searching ability and convergence rate of the solution by the combination of multiple composite trial vectors and control parameter settings. Its great generality makes itself applicable to selective harmonic elimination PWM and synchronous harmonic optimum PWM as well. This study introduces the basic principles of SHMPWM and CoDE, constructs the constraint and objective functions by means of penalty, and gives detailed solution steps. After getting the switching angle solutions from comparative studies including different switching angle numbers, different modulation degrees, or different optimised PWM methods, the experimental platform finally has been designed and carried out to verify the accuracy and generality of the proposed method.

This study presents the modelling, analysis, and experimental results of a novel capacitive power transfer (CPT) structure with a single coupling capacitor. It is noticed that each charged object has a nature property called self-capacitance, which is a kind of capacitance with respect to infinity. Taking advantage of this property, the conventional CPT structure can be simplified. Instead of using two capacitors to form the closed coupling loop, one of them is replaced by two metallic blocks with relatively big self-capacitances. Even though there is no physical coupling between the two blocks, they can be considered as virtually connected through their self-capacitances to infinity, which forms the return route for the proposed CPT structure. To achieve precise analysis, the detailed circuit model is established with the consideration of self-capacitances for both the blocks and coupling plates. Moreover, the results of the applications with attached blocks replaced by robust reference grounds (RRG) are also analysed in order to extend the proposed structure to more scenarios. System performances with and without RRG are compared. Experiments with different capacitor plate sizes at various transfer distances are also conducted. Both the theoretical analysis and experimental results indicate the effectiveness of the proposed structure.

In this article, a variable sliding surface-based output voltage tracking controller is proposed for three-phase rectifiers driven by the pulse-width modulation technique. A systematical multi-variable approach is used for deriving the control law, considering the not only non-linearity but also parametric uncertainties. The proposed method has two features. First, the non-linear first-order disturbance observers are introduced to enable for the control law to exponentially recover the desirable tracking performance without any offset-errors in the sliding mode. Second, the self-tuning algorithm is designed to update the sliding surface to enhance the output voltage tracking performance in transient periods. The performance of the proposed method is experimentally demonstrated by using a 3-kW three-phase rectifier.

High-order repetitive control can deal with period variation. An augmented second-order repetitive control (RC) scheme is presented to improve system performance under grid frequency variation. Firstly, the relationship between proportional-integral/inertial, multiple-resonant, multi-quasi-resonant control, and second-order RC is analysed. The weight range of second-order RC is discussed. Then, a second-order RC approach augmented by proportional control is proposed for a single-phase grid-tied inverter. Experiments are provided to verify the superiority of second-order RC compared with single-order RC under frequency variation.

A sensorless current-sharing strategy for two-phase and multiphase input-parallel output-parallel (IPOP) DC–DC converters is proposed here. A dual-active-bridge (DAB) DC–DC converter is chosen as the basic DC–DC converter. With this strategy in two-phase IPOP DAB DC–DC converters, the parameter mismatches between phases are estimated by perturbing the duty cycle in one phase and measuring the changes of duty cycles in both phases, then the duty cycles are adjusted to compensate the mismatches, thus achieving current sharing without current sensor. With this strategy in multiphase IPOP DAB DC–DC converters, by perturbing the duty cycles in (N − 1) out of N phases in turn and measuring the changes of duty cycles, respectively, the parameter mismatches among phases are estimated. According to the mismatches, a set of variables, which are proportional to the per-phase output currents, are calculated. Then with a current-sharing regulator, parameter mismatches are compensated, thus achieving current sharing without current sensor. The validity and feasibility of the proposed sensorless current-sharing strategy are verified through both simulation and prototype experimental results.