This work presents a review of new concepts and trends to push silicon power MOSFETs beyond their switching boundaries. The multiple issues encountered when increasing switching power loss and slew rate are thoroughly explained. Afterwards, a large variety of solutions are proposed in silicon technologies, all of them being experimentally proven and elucidated by physics-based simulations. Among these solutions, co-integrated snubbers, induced avalanche operation, local charge balance, tapered trenches, and cascoded configuration are suggested for low- and high-voltage power MOSFETs.

Low-voltage power metal–oxide–semiconductor field-effect transistors (MOSFETs) based on charge compensation using a field plate offer a significant reduction of the area-specific on-resistance. The extension of their blocking capability into the so-called medium-voltage range of 150–300 V promises devices with excellent properties being attractive for a wide range of applications. There are two approaches how this voltage-range extension can be realised. Both concepts are linked to different device performance and different development effort. This study discusses both concepts using the example of the 150 V device class and compares the performance gained at the device and application level.

Recent progress in insulated gate bipolar transistor (IGBT) development is reviewed. Highlighted issues range from technological aspects such as special processes suitable for thin-wafer-processing, through the advanced cell and vertical concepts to approaches for improved IGBT ruggedness. Latest advancements regarding thermal management in both modules and discrete chips are also addressed.

A novel structure called the shorted-anode super-junction trench clustered insulated gate bipolar transistor (SA-SJ-TCIGBT) is proposed and demonstrated through numerical simulations in 1.2 kV, field-stop technology. This device is based on the SJ-TCIGBT concept. In the SA-SJ-TCIGBT structure, due to the introduction of a segmented n⁺-anode, the device can operate in both forward conducting mode and freewheeling diode mode without any snap back in the current–voltage characteristics. In comparison to the SJ-TCIGBT structure, the proposed device shows significant improvement in trade-off relationship between forward voltage drop and switch off energy losses. Simulation results show that 25% decrease in switching energy losses can be achieved. Moreover, the tail current is effectively reduced without any increase in the overshoot voltage. Detailed two-dimensional modelling of the structure shows that significant amount of excess electrons are extracted through the SA structure during turn-off process.

This study presents improvements introduced in a behavioural electro-thermal model of silicon carbide merged PIN-Schottky (SiC MPS) diodes, aimed at a better representation of device characteristics for a more accurate prediction of power dissipation. In the electrical domain, the junction capacitance model has been thoroughly validated with a new parameter extraction procedure, yielding realistic values of the turn-off charge as well as current and voltage waveforms for various operating conditions, which is crucial for dynamic loss evaluation. The validity of the thermal sub-model has been extended by reflecting the temperature dependence of thermal conductivity. As a result, temperature evolution on both the long and short time scales is properly computed, providing correct on-state voltage drop and on-state power loss results. Device behaviour with a heat sink attached is also correctly simulated.

GaN-based transistors are promising devices for power switching applications, but their unique properties require careful design of the circuit in order to achieve the best performance and reliability. The first part will focus on the characterisation of deep-level effects in enhancement- and depletion-mode HEMTs, which limit the performance of the transistor. Threshold voltage instabilities in MIS-HEMT structures, caused by charge trapping under the gate, and their dependence on SiN acting as the gate dielectric will be reviewed. ON-resistance increase, caused by charge trapping in the gate–drain access region, will then be discussed in normally off gate injection transistors, as well as the effect of the switching frequency on the trapping–de-trapping equilibrium condition. The second part of the paper will discuss possible failure modes related to operating conditions, starting with the oxidation of the surface and the inverse piezoelectric effect at high gate–drain voltage. To have a complete picture of high-field effects, the gate dielectric and passivation robustness will be investigated. Time-dependent degradation will then be analysed in both gate reverse and forward-bias conditions. Finally, failures related to off-state stress and to power dissipation and electric field during an ESD event in AlGaN/GaN-HEMTs will be discussed.

p-Channel gallium nitride (GaN) metal–oxide–semiconductor heterostructure field-effect transistors utilising a polarisation induced two-dimensional hole gas operate inherently in depletion mode. The condition for their conversion to enhancement-mode operation is examined via analytical expressions for the threshold voltage and verified via technology computer-aided design (TCAD) simulations. Between the two heterostructures: (i) conventional GaN/aluminium GaN (AlGaN)/GaN and (ii) alternate AlGaN/GaN/AlGaN/GaN examined in this work, the authors demonstrate at higher threshold voltage (), the alternate heterostructure can potentially achieve a higher on-current by a factor of 2 of (), without degradation in the on–off-current ratio, expected ideally to be of the order of .

This study presents monolithically integrated power circuits, fabricated in a high-voltage GaN-on-Si heterojunction technology. Different advanced concepts are presented and compared with solutions found in the literature. High switching transition slew rates are demonstrated by means of a monolithic power circuit with integrated gate driver. A highly linear temperature sensor is integrated in a GaN-high-electron-mobility transistor (HEMT) power device for the 600 V class and on-state resistance of 53 mΩ. An area-efficient HEMT structure with integrated freewheeling diodes is presented. This structure is applied in a monolithic multilevel converter chip, as well as in a 600 V class half-bridge chip. The multilevel chip is integrated by an advanced printed circuit board embedding technology and tested in inverter operation with a mains voltage output of 120 V_RMS. The performance of the half-bridge is demonstrated in a synchronous buck converter operation from 400 to 200 V and with a switching frequency of 3 MHz.

Gallium nitride (GaN)-based P-channel (Pch) and N-channel (Nch) metal–oxide–semiconductor field-effect transistors (MOSFETs) with normally off operations were realised. Both Pch and Nch MOSFETs were monolithically fabricated in a polarisation-junction platform wafer. The platform wafer was constructed with a GaN/aluminium GaN/GaN double heterostructure, which has both two-dimensional hole gas (2DHG) and 2D electron gas (2DEG). The drain currents of Pch and Nch MOSFETs flow through 2DHG and 2DEG, respectively. The threshold gate voltages of the fabricated Pch and Nch MOSFETs were −2.7 and 6.7 V, respectively. It was shown that the threshold voltage and the on-state resistance of the Pch MOSFET can be controlled by adjusting the 2DEG potential. Furthermore, using Pch and Nch MOSFETs, complementary MOS inverter operation was demonstrated.

Diamond p-i-n diodes are one of the most advanced and promising diamond devices for high-power applications. The electrical characteristics of diamond p-i-n diodes have been extensively investigated in the static state, but their switching properties are unknown, and the recovery waveform is the main concern. This study highlights the switching properties of diamond p-i-n diodes used as freewheeling diodes in a clamped inductive switching circuit. The recovery waveform was measured by a wide range of conduction current, reverse blocking voltage, and switching speed. For the basic device design used (without edge termination), the p-i-n diode could be switched from a conducting state at 850 A/cm² to a blocking state at 400 V. The reverse recovery time was <150 ns. The reverse-recovery depends on the on-state current level, reverse voltage, and switching rate, illustrated the fast switching of diamond p-i-n diodes.

Diode-clamped and cascaded H-bridge multilevel inverters are two of the main multilevel inverter topologies; each has its distinct advantages and drawbacks. Regarding the latter, cascaded H-bridge inverters require multiple separate dc sources, whereas (semi-active) diode-clamped inverters contain capacitors that require a means to balance their voltages. This paper investigates a hybrid-topology inverter, comprising a single-phase five-level semi-active diode-clamped inverter and a single-phase cascaded H-bridge inverter with their outputs connected in series, as one way to mitigate the drawbacks of each topology. The proposed control scheme for this inverter operates the switches at fundamental frequency to achieve capacitor voltage-balancing while keeping the switching losses low. Moreover, the step-angles are designed for the 13-level and 11-level output voltage waveform cases (as examples) for a fixed modulation index to achieve optimal total harmonic distortion. Furthermore, the scheme also achieves capacitor voltage-balancing for modulation indices that are close to the optimal modulation index, and for a wide range of load power factors, albeit at the cost of increased output voltage distortion. Simulation results are presented to help explain the processes of capacitor recharging and voltage-balancing, while experimental results are shown as verification of the expected behaviour of this inverter and the proposed control scheme.

Multilevel inverters (MLIs) generating high-quality voltage waveforms are playing a significant role in renewable energy applications. However, the requirement of higher number of power devices, complex pulse-width-modulation (PWM) and voltage unbalancing issues are the impediments associated with their direct usage. Consequently, several attempts to devise MLIs with lesser number of overall components are witnessed. This study focuses on developing a nine-level inverter comprising of a single transformer and reduced component count. An optimisation of the number of transformers and their turn's ratio for a given number of voltage levels resulting in the least number of switches is investigated and deliberated in detail. Besides, an uncomplicated logic gate-based PWM strategy is developed for generating the gating signals of switches using simple Boolean logic relations. A detailed comparison with other recommended MLI topologies is presented to highlight the notable features of the proposed topology. Simulation results obtained using the model developed in MATLAB/Simulink along with the experimental measurements obtained from a downscale prototype is presented to validate the practicability, effectiveness, and viability of the proposed topology. An explicit agreement among the simulation and experimental results is observed.

In modern portable devices, except during short periods of busy time, application processors work at low-power state most of the time to prolong battery life. Thus, high efficiency and low consumption are essential for their power management under light-load conditions. This study presents a dual-phase DC–DC buck converter with light-load performance enhancement for power supply. As load decreases, the converter could transfer the adaptive-on-time-based control strategy from pulse-width modulation to pulse-frequency modulation to enhance efficiency. An extra power-save mode is introduced into design to minimise the power consumption at extremely light load. Besides, a novel current-balance circuit with additional offset elimination block is implemented, which results in equal distribution of load current between phases over wide load range. Moreover, instead of a conventional high precision and fast response comparator, a simple comparator with self-calibration is used in zero-current switching circuit to reduce design complexity, as well as to improve light-load efficiency. The converter is fabricated in 0.18-μm Globalfoundry CMOS process. Experimental results show that91% peak efficiency and 6 µA standby quiescent current is achieved. With the aid of mode switching, current-balance and zero-current switching, the light-load performance enhancement is verified by measurements.

Adjustable speed drives (ASD) are widely used in industry for energy savings, where low-cost diode rectifiers are still employed as the front-ends, also for simplicity in control and reliability in operation. However, significant harmonics appear at the grid, which should be tackled according to standards and/or grid-connection rules. If not, a poor power quality will cause the efficiency of the entire system drop. Currently, communication technologies are still not very cost-effective for industrial harmonic control in multiple parallel motor-drive systems. Therefore, this study proposes a harmonic mitigation strategy for multiple ASD systems, where silicon-controlled rectifiers (SCR) with boost converters in the dc-link have been adopted to increase the harmonic-current controllability. More specific, the SCR firing angles are deliberately dispatched among the drive units, which results in certain phase shifts of the SCR currents on purpose. Consequently, the harmonics appearing in the grid current can be mitigated to some extent without communication. The effectiveness is independent of an individual SCR system loading when a number of drives are connected. Simulations are carried out to verify the discussion. Furthermore, to maximize the harmonic cancellation, a customised modulation scheme has been experimentally demonstrated. Both simulation and experimental results have confirmed the analysis.

A gain-scheduled constrained state feedback controller (SFC) for a SiC MOSFET direct current (DC)–DC buck power converter with a non-synchronous control strategy is presented. First, the synthesis process of a gain-scheduled SFC for a control system with a state-dependent parameter is proposed. Next, constraints of important states and control variables are a posteriori introduced into control algorithm to provide satisfactory dynamic behaviour and safe operation of the plant. The boundary values of control signals which provide permissible values of the future state-space variables are derived from the models of power converters that take into account two modes of operation (i.e. charging and discharging mode). The novelty of the proposed approach lies in efficient control algorithm that utilises the gain-scheduled SFC with the parameter-dependent constraint handling method. The designed control algorithm is extensively tested through simulation and experiments at a switching frequency of 36 kHz. The proposed solution is further compared with a conventional cascade control structure based on two proportional integral controllers for voltage and current loops as well as with a non-constrained state feedback control structure to illustrate its performance and low computational complexity.

Fossil fuel prices and air pollution impel many countries to concentrate on renewable energy sources, of which wind energy is considered to be a pillar. Owing to the numerous advantages when compared with its three-phase counterpart, five-phase direct-drive permanent magnet (PM) generators are a key area of focus in power generation with renewable and wind energy systems. The generator output requires a converter, such as an AC–DC rectifier, to match load requirements. The objective of this work is to generate in real time the gating signals of a fully controlled five-phase, line-commutated rectifier, fed from a five-phase PM generator. A mixed-reality environment is used to implement the gating signal generation algorithm for the five-phase rectifier, where the required gating signals are successfully generated, even with some distorted prototype generator voltage waveforms. The performance of the rectifier is investigated practically and validated by using the MATLAB/SIMULINK platform. Moreover, a comparison with a five-phase pulse-width modulated current source rectifier in terms of losses, size, weight, and cost is presented.

Modular multilevel converters (MMCs) become increasingly attractive in high-voltage dc (HVDC) transmission systems. However, the internal poorly damped characteristic can easily lead to low-frequency harmonic resonance, affecting the stability of MMC. In this study, the equivalent model of MMC is established to reveal the low-frequency harmonic resonance, including intrinsic harmonic resonance and potential harmonic resonance. To suppress the harmonic resonance, a circulating current suppressing method based on active damping is proposed to improve the internal damped characteristic. In order to enhance the control effectiveness, the circulating current reference is modified through a dual feedback closed-loop control involving arm voltages and currents as well as the power feedforward loop in the proposed suppression strategy. Proper parameters are designed to apply the reasonable damping characteristic of MMC. Finally, the proposed method is implemented and verified with an MMC-HVDC system in the RT-LAB simulator platform.

Condition monitoring has been recognised as an effective and low-cost method to enhance the reliability and improve the maintainability of power electronic converters. Hybrid model-based monitoring method is an advanced implementation means due to its non-invasive ways. However, the existing hybrid model is not fit for boost-derived converters for its ignorance of the suddenly change in the diode current caused by switching actions. To solve this problem, a correction term is introduced to modify the primary model. The inductor parasitic resistance is considered for higher accuracy and the gate signal sensor is cancelled for lower complexity. In order to verify the modified model, a parameter identification method based on wavelet denoising (WTD) and recursive least squares arithmetic is proposed. Non-ideal factors (noise and voltage spikes) are analysed and the superiority of the proposed parameter identification scheme is verified. Compared to the primary model, the modified model can achieve higher identification accuracy with fewer sensors, which is more suitable for condition monitoring of Boost converters. The proposed model has been successfully substantiated by the simulation and experimental results of a Boost converter.

In recent years, the shunt active power filters (SAPFs) have received much attention for compensating the harmonic pollution and also providing the reactive content. A crucial issue in controlling the SAPF is generating the reference compensating current (RCC). Typical approaches for this purpose are using the discrete Fourier transform (DFT) in the frequency domain or the instantaneous p–q theory and the synchronous reference frame in the time domain. The DFT, however, suffers from the picket-fence effect and spectral leakage. On the other hand, the DFT takes at least one cycle of the nominal frequency. The time-domain methods show a weakness under voltage distortion, which requires prior filtering techniques. The aim of this study is to present a fast yet effective method for generating the RCC for SAPFs. The proposed method, which is based on the matrix pencil method, has a fast dynamic response and works well under distorted and unbalanced voltage. Moreover, the proposed method can estimate the voltage phase accurately; this property enables the algorithm to compensate for both power factor and current unbalance. The effectiveness of the proposed method is verified using simulation and experimental results, and compared with the standard methods.