Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887
banner image
image of Volume 3, Issue 6
Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 3, Issue 6, November 2009

Volumes & issues:

Volume 3, Issue 6

November 2009

Show / Hide details

  • Advances in nanoelectronics circuits and systems

    • Editorial: Advances in nanoelectronics circuits and systems
      Connecting fabrication defects to fault models and SPICE simulations for DNA self-assembled nanoelectronics
      • Author(s): V. Mao ; V. Thusu ; C. Dwyer ; K. Chakrabarty
      • Source: IET Computers & Digital Techniques, Volume 3, Issue 6, p. 553 –569
      • DOI:  10.1049/iet-cdt.2008.0136
      • Type: Article
      • + Show details - Hide details
      • p. 553 –569 (17)
        The self-assembly of nanoelectronic devices provide an opportunity to achieve unprecedented density and manufacturing scale in the post-Moore's Law era. Bottom-up DNA self-assembly has emerged as a promising technique towards achieving this vision and it has been used to demonstrate precise patterning and functionalisation at resolutions below 20 nm. However, a lack of understanding of fabrication defects and their impact on circuit behaviour are major obstacles to the eventual application of these substrates to circuit design. The authors present a classification of defects observed in our experimental work on self-assembled nanostructures. Atomic force microscope (AFM) images are used to study these defects and determine their relative frequencies. The authors connect these defects to fault models and predict their likely impact on the behaviour of logic gates. Based on simulation program with integrated circuit emphasis simulation data for proposed layouts, the authors conclude that there is a predictive connection between faulty logic behaviour and physical defects for future DNA self-assembled nanoelectronics. This work will be useful in predicting the potential success of defect-tolerance techniques for DNA self-assembled nanoelectronic substrates.
        Add to favourites
        Export citations
      Defect-tolerant N2-transistor structure for reliable nanoelectronic designs
      • Author(s): A.H. El-Maleh ; B.M. Al-Hashimi ; A. Melouki ; F. Khan
      • Source: IET Computers & Digital Techniques, Volume 3, Issue 6, p. 570 –580
      • DOI:  10.1049/iet-cdt.2008.0133
      • Type: Article
      • + Show details - Hide details
      • p. 570 –580 (11)
        Nanodevices-based circuit design will be based on the acceptance that a high percentage of devices in the design will be defective. This study investigates a defect-tolerant technique that adds redundancy at the transistor level and provides built-in immunity to permanent defects (stuck-open, stuck-short and bridges). The proposed technique is based on replacing each transistor by N2-transistor structure (N≥2) that guarantees defect tolerance of all N−1 defects as validated by theoretical analysis and simulation. As demonstrated by extensive simulation results using ISCAS 85 and 89 benchmark circuits, the investigated technique achieves significantly higher defect tolerance than recently reported nanoelectronics defect-tolerant techniques (even with up to 4–5 times more transistor defect probability) and at reduced area overhead. For example, the quadded-transistor structure technique requires nearly half the area of the quadded-logic technique.
        Add to favourites
        Export citations
      Is triple modular redundancy suitable for yield improvement?
      • Author(s): J. Vial ; A. Virazel ; A. Bosio ; P. Girard ; C. Landrault ; S. Pravossoudovitch
      • Source: IET Computers & Digital Techniques, Volume 3, Issue 6, p. 581 –592
      • DOI:  10.1049/iet-cdt.2008.0127
      • Type: Article
      • + Show details - Hide details
      • p. 581 –592 (12)
        With the technology entering the nanodimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. A possible solution to alleviate this problem in the future could consist in using fault-tolerant architectures to tolerate manufacturing defects. In this paper, we consider the classical triple modular redundancy (TMR) as fault-tolerant architecture for yield improvement purposes. Firstly, we compute a set of conditions to be satisfied in order to make use of TMR architectures interesting for yield improvement. Then, we prove that these conditions depend on the testability of the TMR architecture. Thus, we investigate test requirements for TMR architectures and we propose a solution for generating test patterns for this type of architecture. Finally, we propose a new way of implementing the TMR architecture in order to achieve more benefits for yield improvement purpose. This is done by partitioning the logic part and then adding voters between sub-modules. Experimental results are provided on ISCAS'85 and ITC'99 benchmark circuits to demonstrate the efficiency of the proposed approach in terms of yield improvement.
        Add to favourites
        Export citations
      Hybrid NEMS–CMOS integrated circuits: a novel strategy for energy-efficient designs
      • Author(s): H.F. Dadgour  and  K. Banerjee
      • Source: IET Computers & Digital Techniques, Volume 3, Issue 6, p. 593 –608
      • DOI:  10.1049/iet-cdt.2008.0148
      • Type: Article
      • + Show details - Hide details
      • p. 593 –608 (16)
        Substantial increase in gate and sub-threshold leakage of complementary metal-oxide-semiconductor (CMOS) devices is making it extremely challenging to achieve energy-efficient designs while continuing their scaling at the same pace as in the past few decades. Designers constantly sacrifice higher levels of performance to limit the ever-increasing leakage power consumption. One possible solution to tackle the leakage issue, which is proposed in this work, is to integrate nano-electro-mechanical switches (NEMS) with CMOS technology. Hybrid NEMS–CMOS technology takes advantage of both near-zero-leakage characteristics of NEMS devices along with high ON current of CMOS transistors. The feasibility of integration of NEMS switches into a CMOS process is illustrated by a practical process flow. Moreover, co-design of hybrid NEMS–CMOS as low-power dynamic OR gates, static random access memory (SRAM) cells and sleep transistors is explored. Simulation results indicate that such hybrid dynamic OR gates can achieve 60–80% lower switching power and almost zero-leakage power consumption with minor delay penalty. However, the hybrid OR gate outperforms its CMOS counterpart both in terms of delay and switching power consumption with increase in fan-in beyond 12. Additionally, it is shown that a hybrid NEMS–CMOS SRAM cell can achieve almost 8× lower standby leakage power consumption with only minor noise margin and latency cost. Finally, application of NEMS devices as sleep transistors results in up to three orders of magnitude lower OFF current with negligible performance degradation as compared to CMOS sleep switches.
        Add to favourites
        Export citations
      Low-power hybrid complementary metal-oxide-semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mapping
      • Author(s): R.S. Chakraborty ; S. Paul ; Y. Zhou ; S. Bhunia
      • Source: IET Computers & Digital Techniques, Volume 3, Issue 6, p. 609 –624
      • DOI:  10.1049/iet-cdt.2008.0135
      • Type: Article
      • + Show details - Hide details
      • p. 609 –624 (16)
        Conventional programmable fabric implemented in nanoscale complementary metal-oxide-semiconductor (CMOS) technologies suffer from large leakage power dissipation and volatility of the storage cells, which require reconfiguration at each power-on. In this study, the authors present a hybrid field programmable gate array design approach that can leverage on carbon nanotube (CNT)-based nano-electro-mechanical systems (NEMS) switches to implement memory elements leading to significant saving in static power dissipation. Besides, because of the non-volatile nature of the CNT-NEMS switches, the proposed framework eliminates the requirement of reconfiguration on start-up. To implement the programmable interconnects, the authors propose two alternative structures leveraging on non-volatile CNT-NEMS switches. To overcome the high defect density of a nano-fabric, the authors also propose a novel application mapping technique that can take advantage of certain defects modelled as stuck-at faults in the lookup tables (LUTs), thus considerably improving the yield. Simulations show that the proposed CMOS-NEMS LUT-based circuits can achieve an average reduction of 90% in leakage power at iso-performance, compared to the conventional CMOS-based LUT circuits. The proposed defect-aware mapping achieves an average improvement of 87% in the number of mapped functions over conventional mapping for 10% defect rate.
        Add to favourites
        Export citations
      Inversion schemes for sublithographic programmable logic arrays
      • Author(s): B. Gojman ; H. Manem ; G.S. Rose ; A. DeHon
      • Source: IET Computers & Digital Techniques, Volume 3, Issue 6, p. 625 –642
      • DOI:  10.1049/iet-cdt.2008.0128
      • Type: Article
      • + Show details - Hide details
      • p. 625 –642 (18)
        A programmable logic array (PLA) needs its inputs available in both the positive and negative polarities. In lithographic-scale VLSI PLAs, programmable array logics (PALs) and programmable logic devices (PLDs) a buffer and inverter at the PLA input typically produces both polarities from a single polarity input. However, the extreme regularity required for sublithographic designs has driven nanoscale architectures to consider alternate solutions. Consequently, the authors compare three schemes: one based on producing both polarities in a restoration stage (selective inversion), one based on a local inversion stage and one based on a full dual-rail logic implementation. The authors develop a mapping flow for the dual-rail logic and quantify its cost in both logical product terms and physical implementation area and also develop area and timing models for all three schemes. Mapping benchmarks from the Toronto 20 set, the authors are able to show that the local inversion scheme is faster (less than one-fifth the latency), lower energy (one-half the energy) and comparable size to the selective inversion scheme and faster (less than half the latency), smaller (one-third of the area) and lower energy (one-ninth the energy) than the dual-rail scheme.
        Add to favourites
        Export citations
      Adaptive error control for nanometer scale network-on-chip links
      • Author(s): Q. Yu  and  P. Ampadu
      • Source: IET Computers & Digital Techniques, Volume 3, Issue 6, p. 643 –659
      • DOI:  10.1049/iet-cdt.2008.0132
      • Type: Article
      • + Show details - Hide details
      • p. 643 –659 (17)
        The authors present an adaptive error control method for switch-to-switch links in nanoscale networks-on-chip to manage reliability, throughput and energy. Unlike previous works, the proposed method adjusts both error detection and correction simultaneously at runtime. For a given application or predicted noise scenario, an appropriate error control scheme is selected for reliable message transmission. When link conditions degrade, more powerful error detection and correction are temporarily provided to recover the previous message. To achieve this adaptation, the authors create a configurable M-error correction, 2M-error detection code, combined with a hybrid automatic repeat request retransmission policy. Simulation results show that the proposed method can reduce residual flit error rate by over three orders of magnitude and achieve up to 75% higher average throughput compared to other error control methods. Further, average energy per successfully transmitted flit is reduced by up to 15% compared to fixed error control in a 65-nm technology. Compared to a recent adaptive error detection method, a 34% energy reduction can be achieved in high noise environment, at the expense of moderate area overhead.
        Add to favourites
        Export citations

Most viewed content for this Journal

Article
content/journals/iet-cdt
Journal
5
Loading

Most cited content for this Journal

Print this page
This is a required field
Please enter a valid email address