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Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 12, Issue 3, May 2018


Volume 12, Issue 3

May 2018

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    • Energy-efficient fault tolerant technique for deflection routers in two-dimensional mesh Network-on-Chips
      On-chip generation of primary input sequences for multicycle functional broadside tests
      Locality-protected cache allocation scheme with low overhead on GPUs
      Register array-based sum of absolute difference processor with parallel memory system for fast motion estimation
      VLSI design of low-cost and high-precision fixed-point reconfigurable FFT processors
      MPGA: an evolutionary state assignment for dynamic and leakage power reduction in FSM synthesis

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