This work is an additional effort to improve the performance of a four-moduli set residue-based sign detector. The study proposes an arithmetic sign detector for the extended four-moduli set , where n and k are positive integers such that . The proposed arithmetic unit is built using carry-save adders and carry-generation circuits. When compared with the only sign detector available in the literature for a similar moduli set, the proposed one showed very slight reductions in area and power. However, it showed a huge reduction in time delay. Using very-large-scale integration tools, the presented sign detector achieved a reduction of (48.8–59.2)% in time delay.

Hotspots occur frequently in three-dimensional (3D) multi-core processors (3D-MCPs), and they may adversely impact both the reliability and lifetime of a system. The authors present dynamic-voltage-assignment (DVA) strategies that reduce hotspots in and optimise the performance of 3D-MCPs by pre-emptively selecting voltages among low-power and high-performance operating modes. The proposed DVA strategies can be employed in online, thermally constrained task schedulers. Three DVA strategies, random DVA, thermal-aware DVA (TADVA) and TADVA2.0, are proposed to reduce the temperature increase in 3D-MCPs by pre-emptively and dynamically estimating the optimum VAs for all cores in the processor during runtime once the chip begins operating. In particular, TADVA2.0 uses the temperature-variation rates of the cores and takes into account two important thermal behaviours of 3D-MCPs that can effectively limit the temperature increase in 3D-MCPs. Experimental results indicate that, when compared with two previous online thermally constrained task schedulers, the proposed task scheduler with their novel DVA strategy can reduce hotspot occurrences by ∼60% and improve throughput by ∼8%. These results indicate that the proposed TADVA2.0 strategy is an effective technique for suppressing hotspot occurrences and optimising throughput for 3D-MCPs subject to thermal constraints.

Predictive modelling has gained much attention in the last decade, aiming fast evaluation of different design points in design space exploration (DSE) process. However, predictive model construction still requires costly simulations for every unseen program. To reduce the number of simulations, several cross-program prediction schemes have been developed. This study proposes a cross-program predictive scheme for micro-architectural DSE. The scheme measures a set of representative inherent characteristics for the unseen program and compares them against the same characteristics of training programs. Then, based on similarity information, the performance trend of the unseen program is predicted using the predictive models of training programs. As the raw data of the characteristics do not characterise programs in performance space, the authors propose a novel method which transforms the characteristic space into performance space. The proposed method achieves 13.3× speed-up over the program-centric scheme with an average correlation coefficient of 0.92.

Modular multiplication (MM) is the main operation in cryptography algorithms such as elliptic-curve cryptography (ECC) and Rivest–Shamir–Adleman, where repeated MM is used to perform elliptic curve point multiplication and modular exponentiation, respectively. The algorithm for the proposed architecture is derived from the Chinese remainder theorem and performs MM completely within a residue number system (RNS). Moreover, a 40-channel RNS moduli-set is proposed for this architecture to benefit from the short-channel width of the RNS moduli-set. The throughput of the architecture is enhanced by pipelining and pre-computations. The proposed architecture is fabricated as an ASIC using 65-nm CMOS technology. The measurement results are obtained for energy dissipation at different voltage levels from 0.43 to 1.25 V. The maximum throughput of the proposed design is 1037 Mbps while operating at a frequency of 162 MHz with an energy dissipation of 48 nJ. The proposed architecture enables the construction of low-voltage and energy-efficient ECCs.