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Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 11, Issue 6, November 2017


Volume 11, Issue 6

November 2017

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    • LTL transformation modulo positive transitions
      Extending multi-level STT-MRAM cell lifetime by minimising two-step and hard state transitions in hot bits
      Implementation of nMPRA CPU architecture based on preemptive hardware scheduler engine and different scheduling algorithms
      Dependability analysis of cyber physical systems

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