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Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 1, Issue 5, September 2007

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Volume 1, Issue 5

September 2007

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  • Design of circuits and integrated systems

    • Editorial: Design of circuits and integrated systems
      A digital system to emulate wireless networks
      • Author(s): E. Peña ; E. de la Torre ; A. de Castro ; T. Riesgo
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 5, p. 444 –450
      • DOI:  10.1049/iet-cdt:20060055
      • Type: Article
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      • p. 444 –450 (7)
        Evaluation of network protocols and validation of communications-related hardware blocks, like filters or error correction codes, require complex testbench set-ups for real measurements in wireless network systems. Real tests involve costly logistics and instrumentation, while simulation-based approaches may be too slow for long tests. In this paper, the authors present a methodology based on a configurable digital intellectual property (IP) module that performs transmissions at bit-level, emulating the behaviour of a wireless network, allowing, in many cases, the emulation of a complete system on a field programmable gate array (FPGA). The emulation-based system was used to test the integration and performance evaluation of forward error correction (FEC) processing blocks, like Viterbi, and emulated results were compared against Matlab simulations and real laboratory RF measurements. A brief discussion about these three main approaches is presented. Methodology considerations and use cases are included.
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      Towards a configurable SoC MPEG-4 advanced simple profile decoder
      • Author(s): L. García ; G.M. Callico ; D. Barreto ; V. Reyes ; T. Bautista ; A. Nunez
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 5, p. 451 –460
      • DOI:  10.1049/iet-cdt:20060054
      • Type: Article
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      • p. 451 –460 (10)
        The evaluation of various architectural designs to allow low bandwidth digital video decoding and reception over the digital audio broadcasting network, and the problem of how to find and implement an optimal HW/SW partition on a Programmable Logic Device with an embedded ARM9 processor are focused. Profiling and design space exploration techniques are applied to the advanced simple profile of an MPEG-4 decoder, for which an innovative SystemC-based system-level design tool, called CASSE, has been used. Simulations results showed that a throughput of 15 QCIF frames per second can be achieved with a low area and low power implementation. Details of this implementation and where the results differ from simulation are presented.
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      Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems
      • Author(s): M.L. Silva  and  J.C. Ferreira
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 5, p. 461 –471
      • DOI:  10.1049/iet-cdt:20060056
      • Type: Article
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      • p. 461 –471 (11)
        A tool called BitLinker, that creates partially reconfigurable modules from the bitstreams of individual components is described. It is also capable of performing restricted component placement and interconnect routing between the assembled components. The resulting modules are used in applications that exploit partial dynamic reconfiguration. The tool is integrated in a design flow particularly aimed at dynamically reconfigurable platform field-programmable gate arrays (FPGAs). The associated development design flow and a run-time support system that can be used to manage module activation and data communication are described. Evaluation results obtained with a Virtex-II Pro system are also reported.
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      Improving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structures
      • Author(s): R. Chaves  and  L. Sousa
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 5, p. 472 –480
      • DOI:  10.1049/iet-cdt:20060059
      • Type: Article
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      • p. 472 –480 (9)
        Residue number systems (RNS) are non-weighted systems that allow to perform addition, subtraction and multiplication operations concurrently and independently on each residue. The triple moduli set {2n−1, 2n, 2n+1} and its respective extensions have gained unprecedent importance in RNS, mainly because of the simplicity of the arithmetic units for the individual channels and also of the converters to and from RNS. However, there is neither a perfect balance between the various elements of this moduli set nor an exact equivalence in the complexity of the individual arithmetic units for each individual residue. Two complementary approaches have been proposed to improve the efficiency of RNS based on this type of moduli sets: enhancing multipliers modulo 2n+1, which perform the most complex arithmetic operation, and overloading the binary channel in order to obtain a more balanced moduli set. Experimental results show that, when applied together, these techniques can improve the efficiency of the multipliers up to 32%.
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      Charge-based testing BIST for embedded memories
      • Author(s): B. Alorda ; I. de Paul ; J. Segura
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 5, p. 481 –490
      • DOI:  10.1049/iet-cdt:20060058
      • Type: Article
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      • p. 481 –490 (10)
        A BIST architecture is presented to perform charge-based testing (BIST-CBT) on embedded memories where direct access to I/Os is limited. The proposed architecture includes a charge monitor, a functional test algorithm generator (that applies a standard March B algorithm) and output processing circuitry. The method is based on a charge correlation technique validated experimentally on previous works for submicron SRAMs. The testing methodology implementation has two phases: a short pre-characterisation phase performed during manufacturing test to ensure process-variation immunity, and the actual BIST-CBT. Data from the first phase are processed and loaded in the BIST circuitry registers. The proposed embedded BIST circuitry provides a digital output pass/fail flag that signals the result of the functional and BIST charge analysis (both based on the same March algorithms). To demonstrate the viability of the proposed architecture, a prototype is designed that has been implemented in two parts: the charge monitor is the core of the BIST circuitry, and has been developed in 120 nm CMOS technology, whereas the digital processing circuitry has been implemented on a FPGA device.
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      Functional-oriented mask-based built-in self-test
      • Author(s): M.B. Santos  and  J. Paulo Teixeira
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 5, p. 491 –498
      • DOI:  10.1049/iet-cdt:20060073
      • Type: Article
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      • p. 491 –498 (8)
        Built-in self-test (BIST) is a key design-for-testability technique for digital systems in nanometre technologies. BIST design is usually quite intrusive. In fact, BIST-per-scan or BIST-per-clock schemes require the replacement of all circuit registers by modified flip-flops or registers with extra functionality, which may lead to unacceptable area overhead and, especially, performance degradation. However, for some applications, system performance cannot be compromised by BIST insertion. Moreover, many applications have multiple clock domains and need to be self-tested at speed, during product lifetime. The functional-oriented mask-based BIST is proposed as a minimum impact BIST design methodology. The proposed approach uses testability metrics and circuit functionality to iteratively obtain a BIST solution with the required fault coverage (FC). It can be implemented in multiple clock domain designs and lead to short BIST sessions and a limited impact on system performance. A real world case study, for which system performance is critical, is used to demonstrate that high FC values in a sequential circuit can be achieved, operating at-speed with multiple clock signals, with minimum performance degradation and with lower hardware overhead than the one obtained with a BIST-per-scan solution. The case study is a two-clock domain Sync core for the Synchronisation and Link Board of electromagnetic calorimeter and hadron calorimeter detectors of the CERN compact Muon solenoid experiment.
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  • Advances in electronics systems simulation

    • Editorial: Advances in electronics systems simulation
      Simulation and development environment for mobile 3D graphics architectures
      • Author(s): W.-J. Lee ; W.-C. Park ; V.P. Srini ; T.-D. Han
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 5, p. 501 –507
      • DOI:  10.1049/iet-cdt:20050205
      • Type: Article
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      • p. 501 –507 (7)
        This paper describes a simulation and development environment for designing mobile three-dimensional (3D) graphics architectures. The proposed simulation and verification environment (SVE) uses glTrace's ability to intercept and redirect an OpenGL|ES streams. The SVE simulates the behaviour of mobile 3D graphics pipeline during the playback of traces and produces the second geometry trace that can be used as a test vector for the Verilog/hardware discription language RT-level model. An architectural verification can be conducted by comparing the frame-by-frame results. The functionality of the SVE is demonstrated by designing a mobile 3D graphics architecture and implementing the verified architecture on field programmable gate array (FPGA) boards. An application development environment (ADE) is also presented that includes a mobile graphics application programming interface and a device driver interface. The proposed SVE and the ADE could be efficiently used for developing and testing mobile applications, architectural analysis and hardware designs.
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      Modelling and simulation of wireless sensor system for health monitoring using HDL and Simulink® mixed environment
      • Author(s): K. Arshak ; E. Jafer ; D. McDonagh ; C.S. Ibala
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 5, p. 508 –518
      • DOI:  10.1049/iet-cdt:20050206
      • Type: Article
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      • p. 508 –518 (11)
        The aim of this study is to model and design an efficient wireless system that is easy to integrate with other technologies or infrastructures at a low cost. The system would read analogue information recorded by a biomedical sensor in a transmitting unit attached to the patient. The recorded data are converted digitally using analogue-to-digital converter and sent to frequency-shift keying (FSK) transmitter through field programmable gate arrays (FPGAs). Verilog-HDL has been used to implement the required functions of the FPGA, such as bus interfacing, data buffering, compression and data framing. On the other hand, Simulink® software has been used to model and simulate FSK transmitter/receiver architecture suitable for short-range communications. Basically, a two-tone FSK signal is generated and passed through a noisy channel, which is then downconverted to baseband and passed to the frequency-modulating detector to restore the original transmitted bit stream. These illustrate how easily the mixed signal modelling can be well mapped into hardware description language (HDL) and mathematical programming techniques. The developed simulation models are used to explore the design change options. The behavioural HDL design has been interfaced to the Simulink model using system generator in a co-simulation environment, and the overall performance has been verified.
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      Modelling tools built upon the hardware description language foundation
      • Author(s): A. Mantooth ; A. Francis ; Y. Feng ; W. Zheng
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 5, p. 519 –527
      • DOI:  10.1049/iet-cdt:20050213
      • Type: Article
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      • p. 519 –527 (9)
        Hardware description languages (HDLs), mainly Verilog and VHDL including their analogue/mixed-signal (AMS) extensions, represent a significant investment by the electronic design automation community. HDL technology promises productivity advances, such as a medium for intellectual property exchange, model portability, model productivity, improved design collaboration, top-down design for AMS, AMS synthesis and rich mixed-level, mixed-signal simulation for improved simulation throughput. Modelling tools represent a step towards completion of the dwelling electronic design automation community's seek to build upon the HDL foundation. One such environment of tools described here is Paragon. Paragon is described and demonstrated on both behavioural models using multiple HDLs and compact device modelling applications. The various processes and modelling methodologies that are useful in designing and modelling complex mixed-signal circuits and systems are explored. The model creation processes of mixed-signal and mixed-technology systems at various levels of abstraction and hierarchy are described. Creation of compact behavioural models at a more abstract and language-independent level using these modelling methodologies is illustrated.
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      Modelling and simulation techniques for highly integrated, low-power wireless sensor networks
      • Author(s): B. Otis ; S. Gambini ; R. Shah ; D. Steingart ; E. Quévy ; J. Rabaey ; A. Sangiovanni-Vincentelli ; P. Wright
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 5, p. 528 –536
      • DOI:  10.1049/iet-cdt:20050214
      • Type: Article
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      • p. 528 –536 (9)
        The design of state-of-the-art low-power wireless sensor nodes involves the convergence of many technologies and disciplines. Submicron complementary metal oxide semiconductor (CMOS) devices, micro-electro-mechanical system filters, on- and off-chip electromagnetic elements, sensors and thin-film batteries are some of the technologies that will enable pervasive systems such as wireless sensor networks. High system complexity requires the use of many simulation environment during design: algorithm simulators, mechanical finite element analysis, behavioural and transistor-level circuit simulators, electromagnetic (EM) simulators, thin-film battery simulators and network simulators. It is shown that highly integrated, self-contained systems require multiple-domain simulations to uncover complex interactions between domains. Specific examples of block- and system-level design methodologies used in low-power wireless systems are presented here. Bottlenecks in the current methodology will be identified with an eye towards improving the scope and resolution of system-level simulations.
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  • General articles

    • Effectiveness of scan-based delay fault tests in diagnosis of transition faults
      • Author(s): I. Pomeranz  and  S.M. Reddy
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 5, p. 537 –545
      • DOI:  10.1049/iet-cdt:20070029
      • Type: Article
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      • p. 537 –545 (9)
        The effectiveness of various types of scan-based delay fault tests in diagnosis of transition faults is studied. Enhanced scan tests, skewed-load tests, broadside tests, functional broadside tests and a combination of skewed-load and broadside tests are considered. The results indicate, for example, that even if functional broadside tests are used for fault detection to avoid overtesting, the test set should be extended for fault diagnosis by adding other types of tests. Adding a small number of skewed-load tests is especially useful for diagnosis if enhanced scan is not available.
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      Admitting and ejecting flits in wormhole-switched networks on chip
      • Author(s): Z. Lu  and  A. Jantsch
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 5, p. 546 –556
      • DOI:  10.1049/iet-cdt:20050068
      • Type: Article
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      • p. 546 –556 (11)
        Reducing the design complexity of switches is essential for cost reduction and power saving in on-chip networks. In wormhole-switched networks, packets are split into flits which are then admitted into and delivered in the network. When reaching destinations, flits are ejected from the network. Since flit admission, flit delivery and flit ejection interfere with each other directly and indirectly, techniques for admitting and ejecting flits exert a significant impact on network performance and switch cost. Different flit-admission and flit-ejection micro-architectures are investigated. In particular, for flit admission, a novel coupling scheme which binds a flit-admission queue with a physical channel (PC) is presented. This scheme simplifies the switch crossbar from 2p×p to (p+1)×p, where p is the number of PCs per switch. For flit ejection, a p-sink model that uses only p flit sinks to eject flits is proposed. In contrast to an ideal ejection model which requires p · v flit sinks (v is the number of virtual channels per PC), the buffering cost of flit sinks becomes independent of v. The proposed flit-admission and flit-ejection schemes are evaluated with both uniform and locality traffic in a 2D 4×4 mesh network. The results show that both schemes do not degrade network performance in terms of average packet latency and throughput if the flit injection rate is slower than 0.57 flit/cycle/node.
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      Algorithmic-level exploration of discrete signal transforms for partitioning to distributed hardware architectures
      • Author(s): R.A. Arce Nazario ; M. Jimenez ; D. Rodríguez
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 5, p. 557 –564
      • DOI:  10.1049/iet-cdt:20060125
      • Type: Article
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      • p. 557 –564 (8)
        High-level partitioning is an essential process for obtaining effective algorithm implementations to distributed hardware architectures (DHAs). Discrete signal transforms (DST) in general have well-known algorithmic properties that can be exploited to improve their partitioning in hardware implementations. A high-level partitioning methodology which uses formulation-level discrete signal transform properties to guide DST partitioning onto DHAs is introduced. It has been discussed how such characteristics were taken into account to focus design exploration during partitioning. A set of experiments carried to determine the effect of formulation-level properties on solution quality are also presented. Perceived patterns in experimental results were used to generate ‘partition-friendly’ fast Fourier transform (FFT) formulations for DHAs. Results for various FFT sizes achieved over 21% reduction in estimated latency over a general-purpose high-level partitioning method.
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      Memory hierarchy for high-performance and energy-aware reconfigurable systems
      • Author(s): E.P. Ramo ; J. Resano ; D. Mozos ; F. Catthoor
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 5, p. 565 –571
      • DOI:  10.1049/iet-cdt:20060155
      • Type: Article
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      • p. 565 –571 (7)
        Run-time reconfigurable resources present many of the features such as high performance, flexibility and reusability demanded by next generation embedded systems. In addition, many emerging reconfigurable architectures have been optimised for low power. However, carrying out run-time reconfigurations often involves a costly reconfiguration overhead both in execution time and in energy consumption. Only the execution-time overhead was dealt with in the previous work. Here, the approach is significantly extended in order to reduce the reconfiguration energy overhead as well. To this end, a configuration memory hierarchy is proposed, with a shared memory layer consisting of a module optimised for performance combined with a module optimised for energy-efficient accesses. For this hierarchy, the authors have developed a mapping algorithm that decides where to load each configuration in order to achieve significant energy savings without introducing any performance degradation.
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      Enhanced prefix inclusion coding filter-encoding algorithm for packet classification with ternary content addressable memory
      • Author(s): D. Pao ; P. Zhou ; B. Liu ; X. Zhang
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 5, p. 572 –580
      • DOI:  10.1049/iet-cdt:20060226
      • Type: Article
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      • p. 572 –580 (9)
        Filter encoding can effectively enhance the efficiency of ternary content addressable memory (TCAM)-based packet classification. It can minimise the range expansion problem, reduce the TCAM space requirement and improve the lookup rate for IPv6. However, additional complexity will incur inevitably in the filter table update operations. Although the average update cost of the prefix inclusion coding (PIC) scheme is very low, the worst-case update cost can be significantly higher. Major modifications to the PIC scheme to improve its update performance are presented. The new coding scheme is called PIC with segmented domain. By dividing the field value domain into multiple segments, the mapping of field values to code points can be more structural and help avoid massive code-point relocation in the event of new insertions. Moreover, the simplified codeword lookup for the address fields can be implemented with embedded SRAM rather than with TCAM. Consequently, the lookup rate of the search engine can be improved to handle the OC-768 line rate.
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      Design and simulation of reusable IP CORDIC core for special-purpose processors
      • Author(s): T.-Y. Sung  and  H.-C. Hsin
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 5, p. 581 –589
      • DOI:  10.1049/iet-cdt:20060075
      • Type: Article
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      • p. 581 –589 (9)
        Coordinate rotation digital computer (CORDIC) is a well-known algorithm using simple adders and shifters to evaluate various elementary functions. A double rotation CORDIC algorithm with an efficient strategy to predict the rotation direction is proposed for a high-speed sine and cosine generator and complex multiplier. Simulation results show that the computation time can be improved by 37.2%, 42.67% and 46.04% for 16-bit, 32-bit and 64-bit operands, respectively. In addition, the overall power consumption per CORDIC arithmetic computation can be improved by 21.2% and 38.5% for 32-bit and 64-bit operands, respectively. Thus, the proposed double rotation CORDIC processor is suitable for high-speed applications.
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      On-chip bus thermal analysis and optimisation
      • Author(s): F. Wang ; M. De Bole ; X. Wu ; Y. Xie ; N. Vijaykrishnan ; M.J. Irwin
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 5, p. 590 –599
      • DOI:  10.1049/iet-cdt:20060116
      • Type: Article
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      • p. 590 –599 (10)
        As technology scales, increasing clock rates, decreasing interconnect pitch and the introduction of low-k dielectrics have made self-heating of the global interconnects an important issue in VLSI design. Further, high bus temperatures have had a negative impact on the delay and reliability of on-chip interconnects. Energy and thermal models are used to characterise the effects of self-heating on the temperature of on-chip interconnects. The results obtained show that self-heating of on-chip buses contribute significantly to the temperature of the bus, which increases as technology scales, motivating the need to find solutions to mitigate this effect. The theoretical analysis performed shows that spreading switching activities among all bus lines can effectively reduce the peak temperature of the on-chip bus. Based on this observation, a thermal spreading encoding scheme for on-chip buses is proposed to tackle the thermal issue. The results obtained show that this approach is very effective in reducing the transient peak temperature among bus lines, with much less overhead compared with other low-power encoding schemes. This technique can then be combined with low-power encoding schemes to further reduce the on-chip bus temperature.
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      VLSI architecture and chip for combined invisible robust and fragile watermarking
      • Author(s): S.P. Mohanty ; E. Kougianos ; N. Ranganathan
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 5, p. 600 –611
      • DOI:  10.1049/iet-cdt:20070057
      • Type: Article
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      • p. 600 –611 (12)
        Research in digital watermarking is mature. Several software implementations of watermarking algorithms are described in the literature, but few attempts have been made to describe hardware implementations. The ultimate objective of the research is to develop low-power, high- performance, real-time, reliable and secure watermarking systems, which can be achieved through hardware implementations. The development of a very-large-scale integration architecture for a high-performance watermarking chip is presented which can perform both invisible robust and invisible fragile image watermarking in the spatial domain. The watermarking architecture is prototyped in two ways: (i) by using a Xilinx field-programmable gate array and (ii) by building a custom integrated circuit. This prototype is the first watermarking chip with both invisible robust and invisible fragile watermarking capabilities.
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      Fast and memory-efficient invariant computation of ordinary Petri nets
      • Author(s): C.-F. Law ; B.-H. Gwee ; J.S. Chang
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 5, p. 612 –624
      • DOI:  10.1049/iet-cdt:20060071
      • Type: Article
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      • p. 612 –624 (13)
        An efficient implementation of the Fourier-Motzkin (FM) algorithm for computing all non-negative, minimal-support invariants of ordinary Petri nets is proposed. The proposed algorithm is inspired by the observation that for a set S of parallel places (i.e. places that have the same input and output transitions, and the same corresponding arc weights), if there exists an invariant y1 whose support contains p1∈S, then there also exist k–1 invariants yi, i=2, 3,   , k, where k=|S|, such that the support of yi contains a place pi∈S. The proposed algorithm exploits this observation by computing only y1 and then generating the other corresponding invariants through a proposed enumerative process. The tests indicate that on an average, the proposed algorithm is at least 2.2 times faster in execution, and requires at least 1.8 times less memory than other comparable algorithms.
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      Fast INC-XOR codec for low-power address buses
      • Author(s): H. Parandeh-Afshar ; M. Saneei ; A. Afzali-Kusha ; M. Pedram
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 5, p. 625 –631
      • DOI:  10.1049/iet-cdt:20070056
      • Type: Article
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      • p. 625 –631 (7)
        A very fast and low-power address bus encoder, whose critical path delay and area are only weakly dependent on the address bus width, is presented. Although the encoding algorithm of the proposed structure is the same as the INC-XOR encoding, its encoder and decoder architectures, called DX, are much faster. The DX architecture implements the INC-XOR encoding partially (partial DX architecture) or fully (registered DX architecture). The partial implementation, which is faster and consumes less power and silicon area, is appropriate for cases where the size of the basic block (sequential addresses without branches or jumps) is bounded, for example, by 256. The registered DX architecture uses a multi-stage pipelined structure with pseudo-incrementers to reduce the combinational delay of each pipeline stage. The two DX implementations (partial and registered) are compared with three conventional implementations of INC-XOR realised using the ripple carry, the carry look-ahead and Sklansky prefix incrementers. The results of the critical path delay, gate count, power-delay product and energy-delay product show considerable improvements over the conventional implementations.
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      High-performance scalable bidirectional mixed radix-2n serial–serial multipliers
      • Author(s): A. Almiladi ; M.K. Ibrahim ; M. Al-Akidi ; A. Aggoun
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 5, p. 632 –639
      • DOI:  10.1049/iet-cdt:20060107
      • Type: Article
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      • p. 632 –639 (8)
        Two new high-performance bidirectional mixed radix-2n serial–serial multipliers are presented. The new designs have improved the area–time performance by ∼31% when compared with existing radix-2n serial–serial multipliers. The second design is the first twin–pipe bidirectional radix-2n serial–serial multiplier reported in the literature. The twin-pipe multiplier can be used to perform two successive K-digit multiplications in 2K+6 cycles without truncating the results. As a consequence, new data can be fed into the multiplier every K+3 cycles. Both proposed designs possess the scalability feature that is missing in existing radix-2n serial–serial multipliers because of the storage elements, which depend on the number of digits needed at the front-end to ensure correct functionality. As a final remark, another significant aspect of the proposed mixed radix-2n serial–serial architecture and its twin–pipe version is that they can be pipelined to the bit–level and give the designer the flexibility to obtain the best trade–off between throughput rate and hardware cost by varying the digit size and the number of pipelining levels.
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      Hardware platform for software-defined WCDMA/OFDM baseband receiver implementation
      • Author(s): L. Harju  and  J. Nurmi
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 5, p. 640 –652
      • DOI:  10.1049/iet-cdt:20060013
      • Type: Article
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      • p. 640 –652 (13)
        Wireless communications are evolving towards multi-standard systems. As multiple radio technologies need to be integrated into a single mobile terminal, the complexity of the transceiver increases considerably. Programmable architectures and re-use of hardware and software are good methods for tackling this complexity. A programmable hardware platform is presented that enables software-defined implementation of wideband code division multiple access (WCDMA) and orthogonal frequency division multiplexing (OFDM) baseband receivers. The platform is composed of a reduced instruction set computer (RISC) core and three coprocessors. An analysis of the WCDMA and OFDM receiver algorithms shows that the algorithms employ many similar computation kernels, which can be used as functional building blocks in the dual-mode receiver implementation. The programming interface of the proposed platform does not require low-level programming or language extensions, which facilitates productive software development. SystemC-based functional simulations were carried out to find the minimum operation frequency of the platform in different modes and the power consumption was measured with gate-level simulations.
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      Energy-delay efficient test

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